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Programmable logic device including multipliers and configurations thereof to reduce resource utilization 원문보기

IPC분류정보
국가/구분 United States(US) Patent 등록
국제특허분류(IPC7판)
  • G06F-007/38
출원번호 US-0319846 (2005-12-28)
발명자 / 주소
  • Langhammer,Martin
  • Hwang,Chiao Kai
  • Starr,Gregory
출원인 / 주소
  • Altera Corporation
대리인 / 주소
    Fish & Neave IP Group of Ropes & Gray LLP
인용정보 피인용 횟수 : 6  인용 특허 : 67

초록

초록이 없습니다.

대표청구항

대표청구항이 없습니다.

이 특허에 인용된 특허 (67)

  1. De Lange Willem, Apparatus and method for programmable delays using a boundary-scan chain.
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  2. Rajski Janusz ; Tyszer Jerzy,PLX, Arithmetic built-in self test of multiple scan-based integrated circuits.
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  3. Rajski, Janusz; Tyszer, Jerzy, Arithmetic built-in self-test of multiple scan-based integrated circuits.
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  4. Perner Frederick A., Arithmetic cell for field programmable devices.
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  5. Wern-Yan Koe, Combinational test pattern generation method and apparatus.
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  6. Wedgwood Janet E. (Bethpage NY) Petrsoric John F. (New Hyde Park NY), Complex adaptive fir filter.
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  7. Brian C. Faith ; Thomas Oelsner GB; Gary N. Lai, Configurable computational unit embedded in a programmable device.
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  8. Ramamurthy Srinivas ; Berger Neal ; Fahey ; Jr. James,FRX ; Gongwer Geoffrey S. ; Saiki William J. ; Tam Eugene Jinglun, Configuration control in a programmable logic device using non-volatile elements.
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  9. Okamoto Toshiya (Souraku-gun JPX), Data driven type digital filter unit and data driven type information processor including the same.
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  10. Langhammer, Martin; Starr, Gregory; Hwang, Chiao Kai, Devices and methods with programmable logic and digital signal processing regions.
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  11. Leung Ka Yin (Austin TX), Digital filter with decimated frequency response.
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  12. Takano Koji,JPX ; Nagao Fumiaki,JPX, Digital filters.
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  13. Takeuchi Sumitaka (Hyogo JPX) Okada Keisuke (Hyogo JPX), Digital finite impulse response filter and method.
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  14. Staszewski Robert B., Digital finite-impulse-response (FIR) filter with a modified architecture based on high order Radix-N numbering.
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  15. Henry A. Davis, Digital signal processor having enhanced utilization of multiply accumulate (MAC) stage and method.
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  16. Conway, Thomas; Byrne, Jason, Efficient interpolator for high speed timing recovery.
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  17. Andrew J. Miller GB, FPGA implemented bit-serial multiplier and infinite impulse response.
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  18. Nelson David A. (Fort Collins CO), Fast high precision discrete-time analog finite impulse response filter.
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  19. New Bernard J., Field programmable gate array with distributed gate-array functionality.
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  20. Khoury John M., Finite impulse response filter.
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  21. Khoury John M., Finite impulse response filter.
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  22. Quievy Didier (Massy FRX) Desjouis Francis (Maintenon FRX), Frequency multiplier with programmable order of multiplication.
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  23. Lloyd C. Cox ; Gary A. Gramlich ; Robert M. Baker ; Stephen Freeman ; Brian P. Neary ; Cynthia R. Krzemien ; Jordan A. Krim ; Luis R. Nunez, General purpose filter.
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  24. Yano Naoka,JPX ; Tamura Naoyuki,JPX, High-efficiency multiplier and multiplying method.
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  25. Baldwin, David Robert; Murphy, Nicholas J. N.; Maund, Andrew Peter; Pontin, Paul; Cooper, Steve, In-circuit test using scan chains.
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  26. Tavana Danesh ; Yee Wilson K. ; Trimberger Stephen M., Integrated circuit with field programmable and application specific logic areas.
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  27. Tony Ngai ; Bruce Pedersen ; Sergey Shumarayev ; James Schleicher ; Wei-Jen Huang ; Michael Hutton ; Victor Maruri ; Rakesh Patel ; Peter J. Kazarian ; Andrew Leaver ; David W. Mendel ; Ji, Interconnection and input/output resources for programmable logic integrated circuit devices.
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  28. Page Joel ; De Angel Edwin ; Lee Wai Laing ; Wang Lei ; Zheng Hong Helena ; Chow Chung-Kai, Linear phase FIR sinc filter with multiplexing.
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  29. Leung Ka Yin ; Swanson Eric J. ; Leung Kafai, Linear phase finite impulse response filter with pre-addition.
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  30. Steele Randy C. (Southlake TX), Logic block for programmable logic devices.
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  31. Tobias David F., Logic system and method employing multiple configurable logic blocks and capable of implementing a state machine using a minimum amount of configurable logic.
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  32. Baeg Sanghyeon, Low cost emulation scheme implemented via clock control using JTAG controller in a scan environment.
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  33. Hoffman Nathaniel,ILX, Method and apparatus for performing N bit by 2*N-1 bit signed multiplication.
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  34. Kojima Hirotsugu ; Shridhar Avadhani, Method and apparatus for reducing the power consumption in a programmable digital signal processor.
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  35. Telikepalli Anil L. N., Multiplier circuit design for a programmable logic device.
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  36. New Bernard J., Multiplier fabric for use in field programmable gate arrays.
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  37. Laprade Kenneth C. (Palm Bay FL), N-clock, n-bit-serial multiplier.
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  38. Dick, Christopher H.; Harris, Frederic J., Narrow-band filter including sigma-delta modulator implemented in a programmable logic device.
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  39. Black, William C.; Das, Bodhisattva; Hassoun, Marwan M.; Lee, Edward K. F., Nonvolatile programmable logic devices.
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  40. Kelem Steven H. ; Lawman Gary R., On-chip logic analysis and method for using the same.
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  41. Trimberger Stephen M., Optimizing and operating a time multiplexed programmable logic device.
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  42. Martin Philippe (Fresnes FRX) Bonnet Thierry (Champigny FRX) Mathieu Yves (Boulogne FRX), Pipeline-type serial multiplier circuit.
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  43. Chan Andrew K. (Palo Alto CA) Birkner John M. (Portola Valley CA) Chua Hua-Thye (Los Altos Hills CA), Programmable application specific integrated circuit and logic cell therefor.
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  44. Chen Oscal T.-C.,TWX ; Wang Jeng-Yih,TWX, Programmable finite impulse response processor with scalable dynamic data range.
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  45. Kolze Paige A. ; Chan Andrew K. ; Apland James A., Programmable integrated circuit having a test circuit for testing the integrity of routing resource structures.
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  46. Cliff Richard G. (Milpitas CA) Reddy Srinivas T. (Santa Clara CA) Raman Rina (Fremont CA) Cope L. Todd (San Jose CA) Huang Joseph (San Jose CA) Pedersen Bruce B. (San Jose CA), Programmable logic array integrated circuit devices.
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  47. Boggs, Mark Steven; Fulton, Temple L.; Hausman, Steve; McNabb, Gary; McNutt, Alan; Stimmel, Steven W., Programmable logic controller customized function call method, system and apparatus.
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  48. Boggs, Mark Steven; Fulton, Temple L.; Hausman, Steve; McNabb, Gary; McNutt, Alan; Stimmel, Steven W., Programmable logic controller method, system and apparatus.
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  49. Jefferson David E. ; McClintock Cameron ; Schleicher James ; Lee Andy L. ; Mejia Manuel ; Pedersen Bruce B. ; Lane Christopher F. ; Cliff Richard G. ; Reddy Srinivas T., Programmable logic device architecture with super-regions having logic regions and a memory region.
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  50. Cliff Richard G. ; Heile Francis B. ; Huang Joseph ; Lee Fung Fung ; McClintock Cameron ; Mendel David W. ; Pedersen Bruce B. ; Reddy Srinivas T. ; Sung Chiakang ; Veenstra Kerry ; Wang Bonnie I., Programmable logic device architectures.
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  51. Lane Christopher F. ; Reddy Srinivas T. ; Cliff Richard G. ; Zaveri Ketan H. ; Pedersen Bruce B. ; Veenstra Kerry, Programmable logic device circuitry for improving multiplier speed and/or efficiency.
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  52. Pedersen Bruce B. ; Shumarayev Sergey ; Huang Wei-Jen ; Chan Vinson ; Brown Stephen,CAX ; Ngai Tony ; Park James, Programmable logic device configured to accommodate multiplication.
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  53. Pedersen Bruce B., Programmable logic device having combinational logic at inputs to logic elements within logic array blocks.
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  54. Patel Rakesh H. (Santa Clara CA) Turner John E. (Santa Cruz CA) Wong Myron W. (San Jose CA), Programmable logic device having multiplexers and demultiplexers randomly connected to global conductors for interconnec.
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  55. Wong Sau-Ching (Hillsborough CA) So Hock-Chuen (Milpitas CA) Kopec ; Jr. Stanley J. (San Jose CA) Hartmann Robert F. (San Jose CA), Programmable logic device with array blocks connected via programmable interconnect.
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  56. James Park ; Wei-Jen Huang ; Tony Ngai ; Bruce B. Pedersen, Programmable logic device with carry look-ahead.
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  57. Zaveri Ketan ; Lane Christopher F. ; Reddy Srinivas T. ; Lee Andy L. ; McClintock Cameron R. ; Pedersen Bruce B., Programmable logic device with circuitry for observing programmable logic circuit signals and for preloading programmable logic circuits.
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  58. Costello John C. (San Jose CA) Patel Rakesh H. (Santa Clara CA), Programmable logic device with logic block outputs coupled to adjacent logic block output multiplexers.
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  59. Langhammer, Martin; Prasad, Nitin, Programmable logic devices with function-specific blocks.
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  60. Steele Randy C. (Scottsdale AZ) Raad Safoin A. (Scottsdale AZ), Programmable summing functions for programmable logic devices.
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  61. Lesea Austin H., Realizing analog-to-digital converter on a digital programmable integrated circuit.
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  62. Fischer Jonathan Herman ; Smith Lane Allen, Recursive digital filter with reset.
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  63. Smith Lane Allen, System for digital filtering in a fixed number of clock cycles.
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  64. Borland David J., System processing unit extended with programmable logic for plurality of functions.
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  65. Trimberger Stephen M. (San Jose CA) Carberry Richard A. (Los Gatos CA) Johnson Robert Anders (San Jose CA) Wong Jennifer (Fremont CA), Time multiplexed programmable logic device.
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  66. Mori Shojiro (Kawasaki JPX), Transfer circuit for operation test of LSI systems.
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  67. Karimi, Farzin; Crosby, Thompson W.; Irrinki, V. Swamy, Use of a scan chain for configuration of BIST unit operation.
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  3. Lerner, Boris, Computing module for efficient FFT and FIR hardware accelerator.
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  4. Burge, Benjamin D.; Carreras, Ricardo F., Convertible filter.
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  5. Burge, Benjamin D.; Carreras, Ricardo F.; Joho, Marcel, Convertible filter.
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  6. Matsuyama, Hideki; Daitou, Masayuki, Microprocessor.
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