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이 특허를 인용한 특허 (3) 인용/피인용 타임라인 분석

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2. Tran, Hau Thien; Cameron, Kelly Brian; Shen, Ba Zhong, Efficient front end memory arrangement to support parallel bit node and check node processing in LDPC (Low Density Parity Check) decoders.

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3. Farjadrad, Ramin; Benyamin, Saied, Efficient message passing scheme of iterative error correcting decoders.

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