이 특허에 인용된 특허 (21) 인용/피인용 타임라인 분석

1. Thakur Randhir P. S. (Boise ID) Mathews Viju K. (Boise ID), Advanced technique to improve the bonding arrangement on silicon surfaces to promote uniform nitridation.

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2. Sato Noriaki (Kawasaki JPX) Mieno Fumitake (Kawasaki JPX), An integrated semiconductor device having a buried semiconductor layer and fabrication method thereof.

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3. Ihantola Heikki,FIX, Apparatus and method for processing of semiconductors, such as silicon chips.

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4. Aoki Kenji (Tokyo JPX), Apparatus for forming a semiconductor crystal.

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5. Sakamoto Mitsuru (Tokyo JPX), Device comprising lower and upper silicon layers as capacitor electrodes and method of manufacturing such devices.

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6. Lemelson Jerome H. (85 Rector St. Metuchen NJ 08840), Electrical device of semi-conducting material with non-conducting areas.

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7. Lee Roger R. (Boise ID), Floating gate memory device having discontinuous gate oxide thickness over the channel region.

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8. Lee Ruojia (Boise ID), High performance sub-micron p-channel transistor with germanium implant.

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9. Sandhu Gurtej S. (Boise ID) Fazan Pierre (Boise ID), High performance thin film transistor (TFT) by solid phase epitaxial regrowth.

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10. Sato Noriaki (Kawasaki JPX) Mieno Fumitake (Kawasaki JPX), Integrated semiconductor device having a buried semiconductor layer and fabrication method thereof.

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11. Thakur Randhir P. S. (Boise ID) Martin Annette L. (Boise ID) Kauffman Ralph E. (Boise ID), Method for fabricating hybrid oxides for thinner gate devices.

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12. Sandhu Gurtej S. (Boise ID) Thakur Randhir P. S. (Boise ID), Method for fabricating stacked layer Si₃N₄ for low leakage high capacitance films using rapi.

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13. Thakur Randir P. S. (Boise ID) Gonzalez Fernando (Boise ID), Method for optimizing thermal budgets in fabricating semiconductors.

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14. Lee Roger R. (Boise ID), Method of making a cell structure for a programmable read only memory device.

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15. Prall Kirk (Boise ID) Pan Pai-Hung (Boise ID) Sharan Sujit (Boise ID), Method of making a field effect transistor having an elevated source and an elevated drain.

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16. Sakamoto Mitsuru (Tokyo JPX), Method of making a semiconductor device comprising lower and upper silicon layers as capacitor electrodes.

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17. Ahmad Aftab (Boise ID) Thakur Randhir P. S. (Boise ID), Method of manufacturing small geometry MOS field-effect transistors having improved barrier layer to hot electron inject.

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18. Bhattacherjee Arya (Newark CA) Koutny William (Santa Clara CA) Shrivastava Ritu (Fremont CA) Rodgers Thurman J. (Woodside CA), Rapid thermal nitridized oxide locos process.

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19. Fujishiro Felix (San Antonio TX) Lee Chang-Ou (San Antonio TX) Vines Landon (Boise ID), Rapid thermal oxidation of silicon in an ozone ambient.

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20. Howell Paul J. (Federal Way WA), Selective epitaxy BiCMOS process.

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21. Mieno Fumitake (Kawasaki JPX) Kurita Kazuyuki (Yokohama JPX) Nakamura Shinji (Yokohama JPX) Shimizu Atuo (Kawasaki JPX), Vapor deposition method for simultaneously growing an epitaxial silicon layer and a polycrystalline silicone layer over.

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