[미국특허]
Semiconductor multipackage module including die and inverted land grid array package stacked over ball grid array package
원문보기
IPC분류정보
국가/구분
United States(US) Patent
등록
국제특허분류(IPC7판)
H01L-023/02
H01L-021/00
H05K-005/00
출원번호
US-0022375
(2004-12-23)
등록번호
US-7253511
(2007-08-07)
발명자
/ 주소
Karnezos,Marcos
Carson,Flynn
Kim,Youngcheol
출원인 / 주소
ChipPAC, Inc.
대리인 / 주소
Haynes Beffel & Wolfeld
인용정보
피인용 횟수 :
37인용 특허 :
109
초록▼
A multipackage module has multiple die of various types and having various functions and, in some embodiments, the module includes a digital processor, an analog device, and memory. A first die, having a comparatively large footprint, is mounted onto first die attach region on a surface of a first p
A multipackage module has multiple die of various types and having various functions and, in some embodiments, the module includes a digital processor, an analog device, and memory. A first die, having a comparatively large footprint, is mounted onto first die attach region on a surface of a first package substrate. A second die, having a significantly smaller footprint, is mounted upon the surface of the first die, on a second die attach region toward one edge of the first die. The first die is electrically connected by wire bonds to conductive traces in the die-attach side of the substrate. The second die is electrically connected by wire bonds to the first package substrate, and may additionally be electrically connected by wire bonds to the first die. In some embodiments a spacer is mounted upon the first die, on a spacer attach region of the surface of the first die that is not within the die attach region, and which may be generally near a margin of the first die. A land grid array (LGA) package is inverted and mounted upon the spacer, with one margin of the LGA package near the edge of the spacer, so that much of the LGA package overhangs the second die. In other embodiments an additional spacer is mounted upon the first die, on a second spacer attach region that is not within the die attach region and not within the first spacer attach region, and the inverted LGA package is mounted upon both spacers. In still other embodiments a first spacer having a thickness approximating the thickness of the second die is mounted in a spacer attach region upon the first die; additional spacers are mounted upon both the first spacer and the second die, and the inverted LGA package is mounted upon the additional spacers. The LGA package is electrically connected to the first package substrate by wire bonds between bond sites on the LGA package and bond sites on the BGA package.
대표청구항▼
What is claimed is: 1. A semiconductor package, comprising a first package die mounted on a first package substrate, the active surface of the first package die facing away from the first package substrate and the first package die being electrically interconnected by wire bonds to conductive trace
What is claimed is: 1. A semiconductor package, comprising a first package die mounted on a first package substrate, the active surface of the first package die facing away from the first package substrate and the first package die being electrically interconnected by wire bonds to conductive traces in the first package substrate, the active surface of the first package die comprising a spacer attach region and a second die attach region; a spacer mounted on the spacer attach region of the active surface of the first package die, wherein the second die attach region is outside the spacer attach region; and a second package, mounted on the spacer and overhanging at least a portion of the second die attach region. 2. The package of claim 1, further comprising a second die mounted on the second die attach region beside the spacer. 3. The package of claim 1 wherein the second package is inverted land grid array package, and wherein the land grid array package is electrically interconnected to the first package by wire bonds between wire bond sites on the upward-facing surface of the second package and wire bond sites on the upward-facing surface of the first substrate. 4. The package of claim 1 wherein the spacer attach region is situated near an edge of the first package die. 5. The package of claim 1 wherein the spacer comprises a solid piece, affixed to the first die using an adhesive. 6. The package of claim 1 wherein the spacer comprises an adhesive spacer. 7. A semiconductor package, comprising a first package die mounted on a first package substrate, the active surface of the first package die facing away from the first package substrate and the first package die being electrically interconnected by wire bonds to conductive traces in the first package substrate, the active surface of the first package die comprising a spacer attach region and a second die attach region; a second die mounted on the die attach region of the active surface of the first package die, wherein the die attach region is outside the spacer attach region; and a second package, mounted on the second die and overhanging at least a portion of the spacer attach region. 8. The package of claim 7, further comprising a spacer mounted on the spacer attach region beside the second die. 9. The package of claim 7 wherein the second die is electrically interconnected by wire bonds to conductive traces on the first package substrate. 10. The package of claim 7 wherein the second die is electrically interconnected by wire bonds to pads on the first package die. 11. The package of claim 9 wherein the second die is additionally electrically interconnected by wire bonds to pads on the first package die. 12. The package of claim 7 wherein the second die attach region is situated away from the center of the active side of the first package die. 13. The package of claim 7 wherein the second die attach region is situated near an edge of the active side of the first package die. 14. The package of claim 13 wherein the second die attach region is situated near a corner of the active side of the first package die. 15. A multipackage module comprising a first package, the first package comprising a first package die mounted on a first package substrate, the active surface of the first package die facing away from the first package substrate and the first package die being electrically interconnected by wire bonds to conductive traces in the first package substrate, the active surface of the first package die having a second die attach region and a spacer attach region; a second die mounted on the second die attach region and a spacer mounted on the spacer attach region; and an inverted land grid array package mounted on the spacer and overhanging at least a portion of the second die. 16. The multipackage module of claim 15 wherein the second die is electrically interconnected by wire bonds to conductive traces on the first package substrate. 17. The multipackage module of claim 16 wherein the second die is additionally electrically interconnected by wire bonds to pads on the first package die. 18. The multipackage module of claim 15 wherein the second die is electrically interconnected by wire bonds to pads on the first package die. 19. The multipackage module of claim 15 wherein the inverted land grid array package is electrically interconnected to the first package substrate by wire bonds between bond sites in conductive traces on the upward-facing surface of the land grid array package and conductive traces on the first package substrate. 20. The multipackage module of claim 15, further comprising a molding over the land grid array package and wires associated therewith, the second die and wires associated therewith, and the exposed portions of the first package and the spacer. 21. The multipackage module of claim 15 wherein the first package is a ball grid array package. 22. The multipackage module of claim 15 wherein the first package die is a digital processor. 23. The multipackage module of claim 15 wherein the second die is an analog device. 24. The multipackage module of claim 15 wherein the land grid array package is a memory package. 25. A multipackage module comprising a first package comprising a first package die and first package substrate, and a LGA package comprising a first LGA package die mounted on a die attach region of a first surface of a LGA substrate, wherein a spacer is mounted over the first package die and the LGA package is inverted and mounted over the spacer, the spacer having a smaller footprint than the LGA package, and wherein the inverted LGA package is electrically interconnected to the first package by wire bonds between interconnect sites on the upward-facing surface of the LGA package and interconnect sites on the upward-facing surface of the first package substrate. 26. The multipackage module of claim 25, wherein the LGA package further comprises a second LGA package die, mounted on a die attach region of the first LGA die and electrically interconnected by wire bonds between die pads along an edge of the second LGA die and sites exposed along an edge of the first surface of the LGA substrate. 27. The multipackage module of claim 26 wherein the second LGA package die is situated such that an edge of the second land grid array package die having die pads is generally parallel to and offset from an edge of the first LGA die having die pads, so that the edge of the second LGA die does not contact the die pads on the first LGA die. 28. The land grid array package of claim 25 wherein the LGA package die and wire bonds are covered by a molding having a surface that constitutes a surface of the LGA package. 29. The multipackage module of claim 25 wherein a part of the LGA package extends beyond the spacer, and wherein the inverted LGA package is situated over the spacer such that the spacer supports a part of the LGA package near an edge of the package having interconnect sites. 30. The multipackage module of claim 25, further comprising a second package die mounted on a second die attach region of the active surface of the first package die. 31. The multipackage module of claim 30, wherein the second die attach region is situated away from the center of the active side of the first package die. 32. The multipackage module of claim 30 wherein the second die attach region is situated near an edge of the surface of the first package die. 33. The multipackage module of claim 30 wherein the second die attach region is situated near a corner of the surface of the first package die. 34. The multipackage module of claim 30 wherein the spacer is situated near an edge of the first package die. 35. The multipackage module of claim 30 wherein the first package die is a digital processor. 36. The multipackage module of claim 30 wherein the first package die and the first package substrate comprise a ball grid array package. 37. The multipackage module of claim 30 wherein the second package die comprises an analog device. 38. The multipackage module of claim 30, further comprising a second spacer mounted on the first package die. 39. The multipackage module of claim 30, further comprising an additional spacer mounted on the second die. 40. The multipackage module of claim 39, wherein the additional spacer comprises a solid piece, affixed to the second die using an adhesive. 41. The multipackage module of claim 40, wherein the additional spacer comprises an adhesive spacer. 42. The multipackage module of claim 25 wherein the LGA package comprises a memory package. 43. The multipackage module of claim 25 wherein the spacer comprises a solid piece, affixed to the first die and to the LGA package using an adhesive. 44. The multipackage module of claim 25 wherein the spacer comprises an adhesive spacer.
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