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System and method for controlling an intergrated circuit to enter a predetermined performance state by skipping all intermediate states based on the determined utilization of the intergrated circuit 원문보기

IPC분류정보
국가/구분 United States(US) Patent 등록
국제특허분류(IPC7판)
  • G06F-001/00
  • G06F-001/32
출원번호 US-0876291 (2001-06-07)
등록번호 US-7254721 (2007-08-07)
발명자 / 주소
  • Tobias,David F.
  • Menezes,Evandro
  • Russell,Richard
  • Altmejd,Morrie
출원인 / 주소
  • Advanced Micro Devices, Inc.
대리인 / 주소
    Zagorin O'Brien Graham LLP
인용정보 피인용 횟수 : 52  인용 특허 : 32

초록

A computer system has multiple performance states. The computer system periodically determines utilization information for the computer system and adjusts the performance state according to the utilization information. If a performance increase is required, the computer system always goes to the max

대표청구항

What is claimed is: 1. A method of managing power consumption in a computing system having a plurality of performance states, including a maximum performance state and a plurality of other performance states that provide successively less performance capability for an integrated circuit, the method

이 특허에 인용된 특허 (32)

  1. Reinhardt Dennis ; Bhat Ketan ; Jackson Robert T. ; Senyk Borys ; Matter Eugene P. ; Gunther Stephen H., Apparatus and method for controlling power usage.
  2. Cooper, Barnes; Arjangrad, Jay, CPU power management based on utilization with lowest performance mode at the mid-utilization range.
  3. Menezes, Evandro; Tobias, David F.; Russell, Richard; Altmejd, Morrie, CPU utilization measurement techniques for use in power management.
  4. Arai Makoto,JPX ; Oda Hiroyuki,JPX ; Ito Hironori,JPX, Cooling mode switching system for CPU.
  5. Hetzler Steven Robert (Sunnyvale CA), Disk drive for portable computer with adaptive demand-driven power management.
  6. Roden Philip A. ; Neil Patrick C. ; Rekieta David W., Dynamic device power management.
  7. Odaohhara, Shigefumi; Naitoh, Arimasa, Dynamic power consumption control for a computer or other electronic apparatus.
  8. Atkinson Lee W., Increased processor performance comparable to a desktop computer from a docked portable computer.
  9. Kawata Kaoru,JPX, Information processing apparatus with CPU-load-based clock frequency.
  10. Buxton Clark L. ; Craycraft Donald G. ; Hawkins Keith G. ; Baum Gary, Integrated processor system adapted for portable personal information devices.
  11. Nagae Toshihide,JPX, Job application distributing system among a plurality of computers, job application distributing method and recording media in which job application distributing program is recorded.
  12. Choquette, Jack; Yeung, Norman K., Method and apparatus for dual issue of program instructions to symmetric multifunctional execution units.
  13. Bikowsky Zeev,ILX, Method and apparatus for operating digital static CMOS components in a very low voltage mode during power-down.
  14. Simmons Laura E. ; Jayavant Rajeev, Method and apparatus for reducing power consumption in digital electronic circuits.
  15. Horden A. Ira ; Gorman Steven D. ; Smith Lionel S., Method and apparatus providing multiple voltages and frequencies selectable based on real time criteria to control pow.
  16. Ohtaki Toshiyuki,JPX, Method for controlling disk-type storage device.
  17. Mittal Millind ; Valentine Robert,ILX, Performance throttling to reduce IC power consumption.
  18. Hetzler Steven Robert, Portable computer with adaptive demand-driven power management.
  19. Cathey David A., Portable computer with selectively operable cooling unit.
  20. Anderson Eric Christopher ; Farhi Henri Hayim, Power management inactivity monitoring using software threads.
  21. Wisor Michael T. (Austin TX) O\Brien Rita M. (Austin TX), Power management system distinguishing between primary and secondary system activity.
  22. Altmejd, Morrie; Russell, Richard; Menezes, Evandro; Tobias, David F., Power state resynchronization.
  23. Fairbanks John P. (Sunnyvale CA) Yuan Andy C. (Saratoga CA), Power supply and oscillator for a computer system providing automatic selection of supply voltage and frequency.
  24. Iwazaki Yasuo,JPX, Power-saving clock control apparatus and method.
  25. Bauer, Eric J.; Yang, Gang, Real-time admission control.
  26. Watts ; Jr. LaVaughn F. (Temple TX) Wallace Steven J. (Temple TX), Real-time power conservation for portable computers.
  27. Culbert Daniel, System and method for dynamic resource management across tasks in real-time operating systems.
  28. Evoy David R., System for reducing the power consumption of a computer system and method therefor.
  29. Lin Richard S. ; Maguire David J. ; Edwards James R. ; Delisle David J., System incorporating hot docking and undocking capabilities without requiring a standby or suspend mode by placing local.
  30. Halahmi Dror,ILX ; Zmora Eitan,ILX ; Goldenberg Chen,ILX, System power saving means and method.
  31. Barnes Cooper, Thermal control within systems having multiple CPU performance states.
  32. Barrus Jeff, User-selectable power management interface with application threshold warnings.

이 특허를 인용한 특허 (52)

  1. Adams, Donald E., Adaptive power management control with performance feedback.
  2. de Cesare, Josh P.; Andrews, Jonathan J., Adjusting device performance based on processing profiles.
  3. Andrews, Jonathan J.; Dasgupta, Romit, Adjusting device performance over multiple time domains.
  4. Bonola, Thomas J.; Faasse, Scott P.; Depew, Kevin G.; Harsany, John S., BIOS-based systems and methods of processor power management.
  5. Prakash, Shyam, Based on natural load determination either adjust processor sleep time or generate artificial load.
  6. Brumett, Jr., Thomas D.; Chen, Ian; Lee, Ilbok; Martinez, Marcelo, Communicating a power control feedback signal.
  7. Tu, Hung-Jan, Computer system capable of dynamically modulating core-voltage and clock frequency of CPU.
  8. Tu, Hung-Jan, Computer system capable of dynamically modulating operation voltage and frequency of CPU.
  9. Brumett, Jr., Thomas D; Chen, Ian; Lee, Ilbok; Martinez, Marcelo, Controlling input power.
  10. Malina, James N.; Hamilton, David M., Data management for a storage device.
  11. Horn, Robert L., Data migration for data storage device.
  12. Flynn, David Walter, Data processing performance control.
  13. McCabe, Timothy J.; Barnes, Edwin D., Device optimized power management.
  14. Boyle, William B.; Meyer, Alan T.; Syu, Mei-Man L., Disk drive steering write data to write cache based on workload.
  15. Prabhakaran, Rajeev; Patel, Jagrut Viliskumar; Choe, Martin (Vyungchon); Parrington, Kyle, Dynamic clock frequency adjustment based on processor load.
  16. Branover, Alexander; Steinman, Maurice B; Bircher, William L, Dynamic performance control of processing nodes.
  17. Gunther, Stephen H.; Greiner, Robert J.; Dai, Xia; Ma, Hung-Piao, Dynamic voltage transitions.
  18. Gunther, Stephen H.; Greiner, Robert J.; Dia, Xia; Ma, Hung-Piao, Dynamic voltage transitions.
  19. Gunther, Stephen H.; Greiner, Robert; Ma, Matthew M.; Dai, Kevin, Dynamic voltage transitions.
  20. Gunther, Stephen H.; Greiner, Robert; Ma, Matthew M.; Dai, Kevin, Dynamic voltage transitions.
  21. Seo,Hyoung Min, Electronic devices and operational methods that change clock frequencies that are applied to a central processing unit and a main system bus.
  22. Wilson, Thomas James; Reeve, Richard James, Gated power management over a system bus.
  23. Manne, Srilatha; Desikan, Rajagopalan; Pant, Sanjay; Kim, Youngtaek, Guardband reduction for multi-core data processor.
  24. Mowry, Anthony C.; Farber, David G.; Austin, Michael J.; Moore, John E., Heat management using power management information.
  25. Meyer, Alan T.; Boyle, William B.; Syu, Mei-Man L.; Wilkins, Virgil V.; Fallone, Robert M., Hybrid drive balancing execution times for non-volatile semiconductor memory and disk.
  26. Boyle, William B.; Stevens, Curtis E.; Coker, Kenny T., Hybrid drive copying disk cache to non-volatile semiconductor memory.
  27. Boyle, William B.; Syu, Mei-Man L.; Wilkins, Virgil V., Hybrid drive migrating data from disk to non-volatile semiconductor memory based on accumulated access time.
  28. Wilkins, Virgil V.; Fallone, Robert M.; Meyer, Alan T.; Boyle, William B., Hybrid drive migrating high workload data from disk to non-volatile semiconductor memory.
  29. Hitaka, Go; Yamagishi, Masahiro, Information processing apparatus and method of controlling operating frequency of an information processing apparatus.
  30. Rusu,Stefan; Ayers,David J.; Burns,James S., Method and apparatus for adjusting the voltage and frequency to minimize power dissipation in a multiprocessor system in response to compute load.
  31. Branover, Alexander; Steinman, Maurice; Bircher, William L., Method and apparatus for demand-based control of processing node performance.
  32. Tobias, David F.; Menezes, Evandro; Russell, Richard; Altmejd, Morrie, Method and apparatus for improving responsiveness of a power management system in a computing device.
  33. Steinman, Maurice B.; Branover, Alexander J.; Krishnan, Guhan, Method for SOC performance and power optimization.
  34. Nijhawan, Vijay; Darnell, Gregory N.; Wu, Wuxian, Methods and systems for managing performance and power utilization of a processor employing a fully multithreaded load threshold.
  35. Nijhawan, Vijay B.; Darnell, Gregory N.; Wu, Wuxian, Methods and systems for managing performance and power utilization of a processor employing a fully-multithreaded load threshold.
  36. Nijhawan, Vijay B.; Darnell, Gregory N.; Wu, Wuxian, Methods and systems for managing performance and power utilization of a processor employing a fully-multithreaded load threshold.
  37. de Cesare, Joshua; Semeria, Bernard; Smith, Michael, Methods and systems for power efficient instruction queue management in a data processing system.
  38. de Cesare, Joshua; Semeria, Bernard Joseph; Smith, Michael, Methods and systems for power management in a data processing system.
  39. de Cesare, Joshua; Semeria, Bernard; Smith, Michael, Methods and systems for power management in a data processing system.
  40. de Cesare, Joshua; Cox, Keith Alan; Begeman, Nathaniel; Hauck, Jerry, Methods and systems to dynamically manage performance states in a data processing system.
  41. de Cesare, Joshua; Cox, Keith; Dyke, Kenneth C., Methods and systems to dynamically manage performance states in a data processing system.
  42. Manne, Srilatha; Pant, Sanjay; Kim, Youngtaek; Schulte, Michael J., Power control for multi-core data processor.
  43. Chen, Huayuan, Power management for data storage device.
  44. Hasfar, Zaihas Amri Fahdzan; Ong, Choo-Bhin; Cheng, Jonathan K., Power management for data storage device.
  45. Hoberman, Barry Alan; Hillman, Daniel L.; Shiell, Jon, Power managers for an integrated circuit.
  46. Hoberman, Barry Alan; Hillman, Daniel L.; Shiell, Jon, Power managers for an integrated circuit.
  47. Deng, Yu, Power saving method, apparatus and communication terminal.
  48. Hovis, William Paul; Blankenburg, Garrett Douglas; Atkinson, Peter Anthony; Ray, Robert James; Hernandez Mojica, Andres Felipe; Boshra-Riad, Samy; Wee, Erng-Sing; Langendorf, Brian Keith, Processor device voltage characterization.
  49. Hovis, William Paul; Blankenburg, Garrett Douglas; Atkinson, Peter Anthony; Ray, Robert James; Hernandez Mojica, Andres Felipe; Boshra-Riad, Samy; Wee, Erng-Sing; Langendorf, Brian Keith, Secure input voltage adjustment in processing devices.
  50. Branover, Alexander J.; Govindan, Madhu Saravana Sibi; Krishnan, Guhan; Mohapatra, Hemant R.; Lueck, Andrew W., System and method for determining a power estimate for an I/O controller based on monitored activity levels and adjusting power limit of processing units by comparing the power estimate with an assigned power limit for the I/O controller.
  51. Naffziger, Samuel D.; Petry, John P.; Bondalapati, Kiran; Hughes, William A., System for processor power limit management.
  52. Fung, Henry T., System, method, and architecture for dynamic server power management and dynamic workload management for multi-server environment.
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