[특허]Integrated imager circuit comprising a monolithic array of single photon avalanche diodes

IPC분류정보
국가/구분	United States(US) Patent 등록
국제특허분류(IPC7판)	H01L-031/00 H01L-027/00
출원번호	US-0353229 (2006-02-14)
등록번호	US-7262402 (2007-08-28)
발명자 / 주소	Niclass,Cristiano Charbon,Edoardo Besse,Pierre Andre Rochas,Alexis
출원인 / 주소	Ecole Polytechnique Federal de Lausanne
대리인 / 주소	Blank Rome LLP
인용정보	피인용 횟수 : 48 인용 특허 : 5

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An integrated imager circuit having a monolithic array of single photon avalanche diodes (SPADs) for capturing an image of a scene when said scene is hit by an optical pulse. The array has a plurality of SPADs connected to 2D readout circuits which determines the intensity of the light reflected by

An integrated imager circuit having a monolithic array of single photon avalanche diodes (SPADs) for capturing an image of a scene when said scene is hit by an optical pulse. The array has a plurality of SPADs connected to 2D readout circuits which determines the intensity of the light reflected by the scene by counting the number of photons received by the SPADs during a period of time. A plurality of SPADs connected to 3D readout circuits determines the distance to the scene by determining the elapsed time between the emission of each pulse and reception of the corresponding reflected photons.

대표청구항 ▼

The invention claimed is: 1. An integrated imager circuit comprising a monolithic array of single photon avalanche diodes (SPADs) for capturing an image of a scene when said scene is hit by an optical pulse, said array comprising: a plurality of first SPADs connected to 2D readout circuits to deter

The invention claimed is: 1. An integrated imager circuit comprising a monolithic array of single photon avalanche diodes (SPADs) for capturing an image of a scene when said scene is hit by an optical pulse, said array comprising: a plurality of first SPADs connected to 2D readout circuits to determine the intensity of the light reflected by said scene by counting the number of photons received by said SPADs during a period of time or by measuring the mean time interval between successive pulses, a plurality of second SPADs connected to 3D readout circuits to determine the distance to said scene by determining the elapsed time between the emission of each pulse and reception of the corresponding reflected photons. 2. The circuit of claim 1, wherein said SPADs are CMOS-implemented and operated in the Geiger mode. 3. The circuit of claim 2, wherein said 2D readout circuits comprise digital counters for counting the number of pulses at the output of the SPADs during a period of time, said digital counter being integrated in said circuit. 4. The circuit of claim 3, wherein said 3D readout circuits comprise time-to-digital converters (TDC) integrated in said circuit. 5. The circuit of claim 1, comprising a plurality of mutually adjacent first SPADs connected to 2D readout circuits and several non adjacent second SPADs connected to 3D readout circuits spread into said array. 6. The circuit of one of claim 1, comprising a plurality of mutually adjacent second SPADs connected to 3D readout circuits and several non adjacent SPADs connected to 2D readout circuits spread into said array. 7. The circuit of claim 1, comprising at least one SPAD connected to a 2D and 3D readout circuit arranged so as to determine both the intensity of light reflected by a scene and the distance to said scene. 8. The circuit of claim 1, said first SPADs being distinct from said second SPADs. 9. The circuit of claim 8, the surface of said first SPADs being different from the surface of said second SPADs. 10. The circuit of claim 1, each 2D readout circuit being located in said array in immediate vicinity of the corresponding first SPADs, each 3D readout circuit being located in said array in immediate vicinity of the corresponding second SPADs. 11. The circuit of one of claim 1, arranged so as to capture a 2D image and a 3D image having different resolutions. 12. An imaging system comprising: the circuit of claim 1, data processing means for computing a representation of the scene captured by said circuit, said representation depending both on the intensity of the light reflected by different portions of the scene and on the distance between said circuit and other portions of said scene. 13. An imaging system comprising: the circuit of claim 1, an optical system on the optical path between said circuit and said scene, wherein the control of focus by said optical system depends on said 3D readout circuit. 14. A method for capturing and processing a digital 2D picture, comprising: capturing a representation of said scene with the circuit of claim 1, said representation including a 2D brightness map of said scene as well as depth indication for indicating the distance to some portions of said scene, automatically isolating areas of said 2D brightness map based on said depth indication, separately processing said isolated areas. 15. A method for capturing an image of a scene, comprising: illuminating said scene with an optical pulse, determining the intensity of light reflected by different portions of said scene by counting the number of photons received by a first plurality of single photon avalanche diodes (SPADs) during a period of time, or by measuring the time intervals between successive pulses determining by a second plurality of SPADs the distance to different portions of said scene by counting the elapsed time between the emission of each pulse and reception of the corresponding reflected photons, wherein said first and second plurality of SPADs are in a monolithic array. 16. A circuit comprising a monolithic array of single photon avalanche diodes (SPADs) operating in the Geiger mode for capturing an image of a scene, said array comprising: a plurality of first SPADs associated with counting means for counting the number of optical pulses at the output of the first SPADs, so as to determine the brightness, a plurality of second SPADs associated with means for determining the elapsed time between the emission of each optical pulse and reception of the corresponding reflected photons. 17. A monolithic integrated circuit comprising: an array of CMOS implemented single photon avalanche diodes (SPADs), a plurality of 2D readout circuits to determine the intensity of light received by at least some of said SPADs, a plurality of 3D readout circuits to determine the elapsed time between emission and reception of the optical pulses by at least some of said SPADs.

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[미국특허] Integrated imager circuit comprising a monolithic array of single photon avalanche diodes 원문보기

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[미국특허] Integrated imager circuit comprising a monolithic array of single photon avalanche diodes 원문보기

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이 특허에 인용된 특허 (5) 인용/피인용 타임라인 분석

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