IPC분류정보
국가/구분 |
United States(US) Patent
등록
|
국제특허분류(IPC7판) |
|
출원번호 |
US-0337153
(2003-01-02)
|
등록번호 |
US-7263759
(2007-09-04)
|
우선권정보 |
IT-TO99A1148(1999-12-23) |
발명자
/ 주소 |
- Marino,Filippo
- Capici,Salvatore
|
출원인 / 주소 |
- STMicroelectronics S.r.l.
|
대리인 / 주소 |
|
인용정보 |
피인용 횟수 :
1 인용 특허 :
7 |
초록
▼
A method of making and testing an electronic device that includes providing first and second external pins, first and second pads on the substrate connected to the first external pin by respective bonding wires, and third and fourth pads on the substrate connected to the second external pin respecti
A method of making and testing an electronic device that includes providing first and second external pins, first and second pads on the substrate connected to the first external pin by respective bonding wires, and third and fourth pads on the substrate connected to the second external pin respective bonding wires, and to a first common line by respective resistors. With a circuit configuration of this type, the intactness of the bonding wires can easily be checked by carrying out a simple resistance measurement between the first and the second external pin.
대표청구항
▼
The invention claimed is: 1. A method for manufacturing an electronic device to enable detection of connection failures in the device by resistance measuring, comprising: providing a first, a second, and at least a third pad on a semiconductor substrate; providing a first and at least a second exte
The invention claimed is: 1. A method for manufacturing an electronic device to enable detection of connection failures in the device by resistance measuring, comprising: providing a first, a second, and at least a third pad on a semiconductor substrate; providing a first and at least a second external pin on a support structure external to the substrate; bonding a first bonding wire between said first pad and said first external pin, a second bonding wire between said second pad and said first external pin, and a third bonding wire between said third pad and said second external pin, said first, second, and third bonding wires physically contacting only their pads and pins; providing a first and at least a second electronic component and having respectively a first and a second electrical resistance on the semiconductor substrate; connecting first terminals of said first and second electronic component respectively to said first and to said second pad, and second terminals of said first and second component to a first node; and connecting said third pad to said first node to enable detection of connection failures in the bonding wires by resistance measuring at the pads. 2. The manufacturing method of claim 1, further comprising: providing a fourth pad; bonding a fourth bonding wire in physical contact with only said fourth pad and said second external pin; providing a third and at least a fourth electronic component having respectively a third and a fourth electrical resistance; and connecting first terminals of said third and fourth electronic component respectively to said third and to said fourth pad, and second terminals of said third and fourth components to said first node. 3. The manufacturing method of claim 2, further comprising: providing a third and at least a fourth external pin; providing a fifth, a sixth and at least a seventh pad; bonding a fifth bonding wire in physical contact with only said fifth pad and said third external pin, a sixth bonding wire in physical contact with only said sixth pad and said third external pin and a seventh bonding wire in physical contact with only said seventh pad and said fourth external pin; providing a fifth and at least a sixth electronic component having respectively a fifth and a sixth electrical resistance; connecting first terminals of said fifth and sixth electronic component respectively to said fifth and said sixth pad, and second terminals of said fifth and sixth electronic component to a second node; and connecting said seventh pad to said second node. 4. The manufacturing method of claim 2, further comprising: providing a transistor having a number of first independent conductivity regions equivalent to the number of said pads connected to said first node; and connecting each of said first conductivity regions to a respective one of said pads connected to said first node. 5. The manufacturing method of claim 2, further comprising: checking the intactness of said bonding wires, said checking the intactness comprising carrying out a resistance measurement between said first and said second external pins. 6. The manufacturing method of claim 3, further comprising: providing an eighth pad; bonding an eighth bonding wire in physical contact with only said eighth pad and said fourth external pin; providing a seventh and an eighth electronic component having respectively a seventh and an eighth electrical resistance; and connecting first terminals of said seventh and eighth electronic components respectively to said seventh and to said eighth pad, and second terminals of said seventh and eighth electronic components to said second node. 7. The manufacturing method of claim 6, wherein providing said electronic components comprises providing resistors, each having a respective electrical resistance. 8. The manufacturing method of claim 6, further comprising: providing a transistor having a number of first independent conductivity regions equivalent to the number of said pads connected to said first node, and a number of second independent conductivity regions equivalent to the number of said pads connected to said second node; connecting each of said first conductivity regions to a respective one of said pads connected to said first node; and connecting each of said second conductivity regions to a respective one of said pads connected to said second node. 9. The manufacturing method of claim 6, farther comprising: checking the intactness of said bonding wires, said checking the intactness comprising the carrying out a resistance measurement between said third and said fourth external pins. 10. The manufacturing method of claim 9, wherein carrying out a resistance measurement comprises carrying out a resistance measurement. 11. A method for manufacturing an electronic device to enable detection of connection failures in the device by resistance measuring, comprising: providing a first, a second and at least a third pad on a semiconductor substrate; providing a first and at least a second external pin on a support structure external to the substrate; bonding a first bonding wire in contact with only said first pad and said first external pin, a second bonding wire in contact with only said second pad and said first external pin, and a third bonding wire in contact with only said third pad and said second external pin; providing a first and at least a second electronic component and having respectively a first and a second electrical resistance of a known value on the semiconductor substrate; connecting first terminals of said first and second electronic component respectively to said first and to said second pad, and second terminals of said first and second component to a first node so that connection failures in the device are detectable by resistance measuring at the pads; and connecting said third pad to said first node. 12. The manufacturing method of claim 11, further comprising: providing a fourth pad; bonding a fourth bonding wire in contact with only said fourth pad and said second external pin; providing a third and at least a fourth electronic component having respectively a third and a fourth electrical resistance; and connecting first terminals of said third and fourth electronic component respectively to said third and to said fourth pad, and second terminals of said third and fourth components to said first node. 13. The manufacturing method of claim 12, further comprising: providing a transistor having a number of first independent conductivity regions equivalent to the number of said pads connected to said first node; and connecting each of said first conductivity regions to a respective one of said pads connected to said first node. 14. The manufacturing method of claim 12, further comprising: checking the intactness of said bonding wires, said checking the intactness comprising carrying out a resistance measurement between said first and said second external pins. 15. The manufacturing method of claim 12, further comprising: providing a third and at least a fourth external pin on the support structure; providing a fifth, a sixth and at least a seventh pad; bonding a fifth bonding wire in contact with only said fifth pad and said third external pin, a sixth bonding wire in contact with only said sixth pad and said third external pin and a seventh bonding wire in contact with only said seventh pad and said fourth external pin; providing a fifth and at least a sixth electronic component having respectively a fifth and a sixth electrical resistance; connecting first terminals of said fifth and sixth electronic component respectively to said fifth and said sixth pad, and second terminals of said fifth and sixth electronic component to a second node; and connecting said seventh pad to said second node. 16. The manufacturing method of claim 15, further comprising: providing an eighth pad; bonding an eighth bonding wire in contact with only said eighth pad and said fourth external pin; providing a seventh and an eighth electronic component having respectively a seventh and an eighth electrical resistance; and connecting first terminals of said seventh and eighth electronic components respectively to said seventh and to said eighth pad, and second terminals of said seventh and eighth electronic components to said second node. 17. The manufacturing method of claim 16, wherein providing said electronic components comprises providing resistors, each having a respective electrical resistance. 18. The manufacturing method of claim 16, further comprising: providing a transistor having a number of first independent conductivity regions equivalent to the number of said pads connected to said first node, and a number of second independent conductivity regions equivalent to the number of said pads connected to said second node; connecting each of said first conductivity regions to a respective one of said pads connected to said first node; and connecting each of said second conductivity regions to a respective one of said pads connected to said second node. 19. The manufacturing method of claim 16, further comprising: checking the intactness of said bonding wires, said checking the intactness comprising the carrying out a resistance measurement between said third and said fourth external pins.
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