초록 ▼

A storage controlling apparatus comprises a store port for holding store data that is transmitted from an arithmetic unit in correspondence with a store request transmitted from an instruction processing device, and is to be written to a cache memory or a memory. The storage controlling apparatus fu

A storage controlling apparatus comprises a store port for holding store data that is transmitted from an arithmetic unit in correspondence with a store request transmitted from an instruction processing device, and is to be written to a cache memory or a memory. The storage controlling apparatus further comprises a data storing unit which receives the store data from the store port, temporarily stores the store data, and comprised between the store port and the cache memory or the memory, and a data write controlling unit which controls a write of the store data from the store port to the data storing unit.

대표청구항 ▼

What is claimed is: 1. A storage controlling apparatus having a store port for holding store data that is transmitted from an arithmetic unit in correspondence with a store request transmitted from an instruction processing device, and that is to be written to a cache memory or a memory as a result

What is claimed is: 1. A storage controlling apparatus having a store port for holding store data that is transmitted from an arithmetic unit in correspondence with a store request transmitted from an instruction processing device, and that is to be written to a cache memory or a memory as a result of the store request, comprising: a data storing unit receiving the store data from the store port, temporarily storing the store data, and comprised between the store port and the cache memory or the memory; and a data write controlling unit controlling a write of the store data from the store port to said data storing unit; and wherein: the store request is divided into a plurality of divided store requests at the store port, and the data storing unit merges the divided store requests transferred from the store port into a merged store request outgoing from the data storing unit; said data storing unit receives the store data from the store port after the instruction processing device commits execution of the store request; said data storing unit comprises a plurality of write buffers which respectively store the store data received from the store port; and said data write controlling unit limits write buffers to a range from a write buffer in which data is stored most recently among the plurality of write buffers to a write buffer ahead by n buffers in an order where data is to be stored, when the instruction processing device simultaneously commits execution of a plurality of (n) store requests, and controls a data write to limited write buffers; and a unit resetting a flag which instructs the store port to write data to said data storing unit upon receipt of a cancellation signal of the store request transmitted from the instruction processing device is further comprised on a side of the store port. 2. A storage controlling apparatus storage controlling apparatus having a store port for holding store data that is transmitted from an arithmetic unit in correspondence with a store request transmitted from an instruction processing device, and that is to be written to a cache memory or a memory as a result of the store request, comprising: a data storing unit receiving the store data from the store port, temporarily storing the store data, and comprised between the store port and the cache memory or the memory; and a data write controlling unit controlling a write of the store data from the store port to said data storing unit; and wherein: the store request is divided into a plurality of divided store requests at the store port, and the data storing unit merges the divided store requests transferred from the store port into a merged store request outgoing from the data storing unit; said data storing unit receives the store data from the store port after the instruction processing device commits execution of the store request; said data storing unit comprises a plurality of write buffers which respectively store the store data received from the store port; said data write controlling unit limits write buffers to being within a range from a write buffer, among the plurality of write buffers, in which data is stored most recently, to a write buffer that is ahead by n buffers in an order in which data is to be stored, when the instruction processing device simultaneously commits execution of a plurality of (n) store requests, and controls a data write to limited write buffers; and said data write controlling unit passes, to the data storing unit, a flag that indicates prohibition of a flush of a cache line, if the store request is determined to be a store request to prohibit the flush of the cache line, which corresponds to the store request, by the time the store request is completed while the store data is held by the store port. 3. The storage controlling apparatus according to claim 1, further comprising: a unit prohibiting said data write controlling unit from merging, in said data storing unit, data stored in said data storing unit in correspondence with a preceding store request, with data from a store port, in correspondence with a next store request according to types of the preceding store request and the next store request when a cancellation of the store request is notified from the instruction processing device; a unit forcibly prohibiting said data write controlling unit from merging, in said data storing unit, data stored in said data storing unit in correspondence with the preceding store request, with data from the store port, in correspondence with the next store request; a unit determining whether or not to permit said data write controlling unit to merge, in said data storing unit, data stored in said data storing unit in correspondence with a preceding store request, with data from the store port, in correspondence with the next store request, and wherein: said data write controlling unit performs data merging in said data storing unit according to a type of a store instruction, even when the data merging is forcibly prohibited; said unit determining whether or not to permit data merging prohibits merging of data already stored in said data storing unit with data within a store port in correspondence with a cancellation signal, when the store port receives the cancellation signal of the store request, which is transmitted from a side of the instruction processing device at the time of thread switching. 4. A storage controlling apparatus having a store port for holding store data that is transmitted from an arithmetic unit in correspondence with a store request transmitted from an instruction processing device, and is to be written to a cache memory or a memory by the store request, comprising: a data storing unit receiving the store data from the store port, temporarily storing the store data, and comprised between the store port and the cache memory or the memory; and a data write controlling unit controlling a write of the store data from the store port to said data storing unit; wherein: the store request is divided into a plurality of divided store requests at the store port, and the data storing unit merges the divided store requests transferred from the store port into a merged store request outgoing from the data storing unit; and a unit resetting a flag which instructs the store port to write data to said data storing unit upon receipt of a cancellation signal of the store request transmitted from the instruction processing device is further comprised on a side of the store port. 5. The storage controlling apparatus according to claim 1, further comprising a memory write controlling unit controlling a data write from said data storing unit to the cache memory or the memory independently of the instruction processing device. 6. The storage controlling apparatus according to claim 1, wherein: said data storing unit comprises one or more write buffers which respectively store the store data received from the store port; and a unit freeing up the store port when the store data is stored in any of the one or more write buffers is further comprised. 7. The storage controlling apparatus according to claim 1, wherein said data storing unit comprises write buffers which respectively store the store data received from the store port by a number according to reply performance of the cache memory or the memory. 8. The storage controlling apparatus according to claim 1, wherein store ports which respectively hold the store data are comprised by a number according to performance of the instruction processing device. 9. The storage controlling apparatus according to claim 1, wherein said data write controlling unit passes a flag indicating a cash hit to said data storing unit, if the store request is determined to hit the cache while the store data is held by the store port. 10. A storage controlling apparatus having a store port for holding store data that is transmitted from an arithmetic unit in correspondence with a store request transmitted from an instruction processing device, and is to be written to a cache memory or a memory by the store request, comprising: a data storing unit receiving the store data from the store port, temporarily storing the store data, and comprised between the store port and the cache memory or the memory; and a data write controlling unit controlling a write of the store data from the store port to said data storing unit; wherein; the store request is divided into a plurality of divided store requests at the store port, and the data storing unit merges the divided store requests transferred from the store port into a merged store request outgoing from the data storing unit; and said data write controlling unit passes a flag, which indicates prohibition of a flush of a cache line, to said data storing unit, if the store request is determined to be a store request to prohibit the flush of the cache line, which corresponds to the store request, by the time the store request is completed while the store data is held by the store port. 11. The storage controlling apparatus according to claim 1, wherein necessary numbers of control flags required to process identical numbers of store requests are respectively held on a side of the store port and a side of said data storing unit. 12. The storage controlling apparatus according to claim 1, further comprising a unit controlling a data write from said data storing unit to a hierarchy to which data is to be written, when the data is to be written to a closest hierarchy or a hierarchy other than the closest hierarchy, if the cache memory is configured by a plurality of hierarchies, and if a store-in method, with which store data is to be written to a hierarchy closest to a central processing unit of a data processing device which includes the storage controlling apparatus among the plurality of hierarchies, is adopted. 13. The storage controlling apparatus according to claim 1, further comprising a unit controlling a data write from said data storing unit to a hierarchy to which data is to be written, when the data is to be written to a closest hierarchy or a second closest hierarchy, if the cache memory is configured by a plurality of hierarchies, and if a store-through method, with which store data is written to a hierarchy closest to a central processing unit of a data processing device which includes the storage controlling apparatus among the plurality of hierarchies depending on need, and the store data is to be written to a second closest hierarchy without fail, is adopted. 14. The storage controlling apparatus according to claim 1, further comprising a unit controlling a data write from said data storing unit to a hierarchy to which data is to be written, even when the data is to be written to any of a plurality of hierarchies of the cache memory, if the cache memory is configured by the plurality of hierarchies, and if both of store-in and store-through methods are used as methods storing data in the cache memory. 15. The storage controlling apparatus according to claim 1, further comprising a unit permitting said data write controlling unit to merge, in said data storing unit, data stored in said data storing unit in correspondence with a preceding store request, with data from a store port in correspondence with a next store request. 16. The storage controlling apparatus according to claim 15, wherein: said data storing unit comprises one or more write buffers which respectively store the store data received from the store port; and the one or more write buffers possess a data width that enables merging of data from the store port, and is wider than a data width possessed by the store port. 17. The storage controlling apparatus according to claim 1, further comprising a unit prohibiting said data write controlling unit from merging, in said data storing unit, data stored in said data storing unit in correspondence with a preceding store request, with data from a store port in correspondence with a next store request according to types of the preceding store request and the next store request. 18. The storage controlling apparatus according to claim 1, further comprising a unit forcibly prohibiting said data write controlling unit from merging, in said data storing unit, data stored in said data storing unit in correspondence with a preceding store request, with data from a store port in correspondence with a next store request. 19. The storage controlling apparatus according to claim 18, wherein said data write controlling unit performs data merging in said data storing unit according to a type of a store instruction, even when the data merging is forcibly prohibited. 20. The storage controlling apparatus according to claim 1, further comprising a unit prohibiting said data write controlling unit from merging, in said data storing unit, data stored in said data storing unit in correspondence with a preceding store request, with data from a store port in correspondence with a next store request, when a cancellation of the store request is notified from the instruction processing device. 21. The storage controlling apparatus according to claim 1, further comprising a unit determining whether or not to permit the store port to perform a store data bypass fetch, which externally provides the store data from the store port in correspondence with an external fetch request before the store data is stored in said data storing unit. 22. The storage controlling apparatus according to claim 21, wherein store data as a bypass permitted candidate is selected by checking matches between addresses and operand lengths of a store request and a fetch request in a determination of whether or not to permit the store data bypass fetch. 23. The storage controlling apparatus according to claim 1, further comprising a unit determining whether or not to permit said data storing unit to perform a store data bypass fetch, which externally provides the store data from said data storing unit in correspondence with an external fetch request before the store data is written to the cache memory or the memory. 24. The storage controlling apparatus according to claim 23, wherein store data as a bypass permitted candidate is selected by making a comparison between byte marks indicating existence positions of data respectively for a store request and a fetch request in units of plural bytes, and by omitting a comparison between identifiers indicating instruction execution orders in a determination of whether or not to permit the store data bypass fetch. 25. The storage controlling apparatus according to claim 24, wherein whether or not to permit the store data bypass fetch is finally determined by making a comparison between the byte marks in units of 1 byte, when the store data bypass fetch of data selected as the bypass permitted candidate is performed. 26. The storage controlling apparatus according to claim 25, further comprising a unit instructing said data storing unit to prohibit the store data bypass fetch, if the store data bypass fetch is not permitted in the comparison between the byte marks in units of 1 byte. 27. The storage controlling apparatus according to claim 1 configures a data processing device controlled by a central processing unit which can perform multithreading. 28. The storage controlling apparatus according to claim 27, wherein the store port and said data storing unit are shared by a plurality of threads in a multithread. 29. The storage controlling apparatus according to claim 27, wherein: a plurality of store ports are comprised; and said data storing unit is shared by a plurality of threads in a multithread, and the store port is exclusively held by each of the plurality of threads. 30. The storage controlling apparatus according to claim 27, wherein: pluralities of store ports and data storing units are respectively comprised; and the pluralities of store ports and data storing units are exclusively held by a plurality of threads in the multithread respectively. 31. The storage controlling apparatus according to claim 27, wherein in correspondence with a cancellation of an inflight store request that starts to be executed at the time of thread switching and is not completed, said data write controlling unit makes said data storing unit write the data held by the store port if the store port already receives a commitment of execution of the store request from the instruction processing device, or frees up the store port without writing its data to the data storing unit if the store port does not receive the commitment of the execution yet. 32. The storage controlling apparatus according to claim 31, wherein said data write controlling unit further frees up a fetch port holding an address and an instruction in correspondence with an external data fetch request at the time of thread switching. 33. The storage controlling apparatus according to claim 27, further comprising a unit holding a thread identifier for identifying each of a plurality of threads in the multithread respectively for the store port and said data storing unit. 34. The storage controlling apparatus according to claim 33, further comprising a unit determining whether or not to permit the store port or said data storing unit to perform a store data bypass fetch, which externally provides the store data from the store port or said data storing unit in correspondence with an external fetch request before the store data is stored in said data storing unit or written to the cache memory or the memory, wherein said unit determining whether or not to permit the store data bypass fetch makes a comparison between an identifier of a thread held for the store port or said data storing unit, and an identifier of a thread requesting a fetch, and prohibits the store data bypass fetch between the threads having different identifiers. 35. The storage controlling apparatus according to claim 33, further comprising a unit determining whether or not to permit said data write controlling unit to merge, in said data storing unit, data stored in said data storing unit in correspondence with a preceding store request, with data from a store port in correspondence with a next store request, wherein said unit determining whether or not to permit data merging makes a comparison between identifiers of threads respectively held for the store port and said data storing unit, and prohibits data merging between the threads having different identifiers. 36. The storage controlling apparatus according to claim 27, further comprising a unit determining whether or not to permit said data write controlling unit to merge, in said data storing unit, data stored in said data storing unit in correspondence with a preceding store request, with data from a store port in correspondence with a next store request, wherein said unit determining whether or not to permit data merging prohibits merging of data already stored in said data storing unit with data within a store port in correspondence with a cancellation signal, when the store port receives the cancellation signal of the store request, which is transmitted from a side of the instruction processing device at the time of thread switching. 37. The storage controlling apparatus according to claim 1, further comprising a unit aligning the store data to a same format as a format when being stored in the memory by the time the store data is stored in said data storing unit. 38. The storage controlling apparatus according to claim 37, wherein said unit aligning the store data comprising a unit performing an alignment process according to an address and an operand length of store data for the store data transmitted from the arithmetic unit, and providing the store data after being aligned to the store port, and a unit performing an alignment process according to an endian for the store data output from the store port, and providing the aligned store data to said data storing unit. 39. The storage controlling apparatus according to claim 38, wherein: a store port and said unit performing the alignment process according to an address and an operand length are arranged in positions close to the arithmetic unit; said data storing unit is arranged in a position close to the cache memory or the memory; and said unit performing the alignment process according to an endian, and said data storing unit are arranged so that a distance between said unit and said data storing unit is made long. 40. The storage controlling apparatus according to claim 1, wherein: said data storing unit comprises one or more write buffers which respectively store the store data received from the store port; and said data write controlling unit performs a control for writing the data output from the store port to a write buffer in which data is stored most recently, or to a write buffer in which data is to be stored next among the plurality of one or more write buffers. 41. The storage controlling apparatus according to claim 1, wherein said data storing unit further comprises a cache line requesting unit entering a cache line request for the store request to a pipeline of the storage controlling apparatus, when the store request misses the cache. 42. The storage controlling apparatus according to claim 1, wherein: said data storing unit comprises a plurality of write buffers which respectively store the store data received from a side of the store port; and a memory write controlling unit performing a control for writing data to the cache memory or the memory from a write buffer other than a write buffer in which data is stored from the store port most recently among the plurality of write buffers is further comprised. 43. The storage controlling apparatus according to claim 1, wherein: said data storing unit comprises a plurality of write buffers which respectively store the store data received from a side of the store port; and a memory write controlling unit making a write buffer, in which data is stored most recently, write data to the cache memory or the memory when the store port becomes empty is further comprised. 44. The storage controlling apparatus according to claim 1, wherein: said data storing unit comprises a plurality of write buffers which respectively store the store data received from a side of the store port; and a memory write controlling unit making a write buffer, in which data is stored most recently, write data, if a succeeding instruction cannot be executed because a data write is not made from the write buffer to the cache memory or the memory is further comprised. 45. The storage controlling apparatus according to claim 1, wherein: said data storing unit comprises a plurality of write buffers which respectively store the store data received from a side of the store port; and a memory write controlling unit making a write buffer, in which data is stored most recently, write data in order to allow a cache line to be freed up, if the cache line for the data stored in the write buffer is externally requested to be freed up is further comprised. 46. The storage controlling apparatus according to claim 1, wherein: said data storing unit comprises a plurality of write buffers which respectively store the store data received from a side of the store port; and a memory write controlling unit making a write buffer, in which data is stored most recently, write data, if merging of data stored in the write buffer with data for a different store request is prohibited is further comprised. 47. A storage controlling apparatus performing a control in correspondence with a store request transmitted from an instruction processing device, comprising: a plurality of buffer units respectively storing store data that is transmitted from an arithmetic unit in correspondence with the store request, and is to be written to a cache memory or a memory; and a memory write controlling unit targeting only a buffer unit in which data is stored earliest among the plurality of buffer units, and performing a control for aborting storage of the store data in the cache memory or the memory, if a length of the store data is shorter than a length of a unit area for which data error management is made in the cache memory or the memory. 48. A storage controlling apparatus storage controlling apparatus having a store port for holding store data that is transmitted from an arithmetic unit in correspondence with a store request transmitted from an instruction processing device, and that is to be written to a cache memory or a memory as a result of the store request, comprising: a data storing unit receiving the store data from the store port, temporarily storing the store data, and comprised between the store port and the cache memory or the memory; and a data write controlling unit controlling a write of the store data from the store port to said data storing unit; a memory write controlling unit, performing a control for writing data to the cache memory or the memory from a write buffer other than a write buffer, from among a plurality of write buffers, in which data is stored most recently from the store port, or making a write buffer, in which data is stored most recently, write data to the cache memory or the memory when the store port becomes empty; or making the write buffer, in which data is stored most recently, write data, if a succeeding instruction cannot be executed because a data write is not made from the write buffer to the cache memory or the memory; or making a write buffer, in which data is stored most recently, write data in order to allow a cache line to be freed up, if the cache line for the data stored in the write buffer is externally requested to be freed up; or making a write buffer, in which data is stored most recently, write data, if merging of data stored in the write buffer with data for a different store request is prohibited, and wherein: the store request is divided into a plurality of divided store requests at the store port, and the data storing unit merges the divided store requests transferred from the store port into a merged store request outgoing from the data storing unit; said data storing unit receives the store data from the store port after the instruction processing device commits execution of the store request; said data storing unit comprises the plurality of write buffers which respectively store the store data received from the store port; and said data write controlling unit limits write buffers to being within a range from a write buffer, among the plurality of write buffers, in which data is stored most recently, to a write buffer that is ahead by n buffers in an order where data is to be stored, when the instruction processing device simultaneously commits execution of a plurality of (n) store requests, and controls a data write to limited write buffers. 49. A storage controlling apparatus having a store port for holding store data that is transmitted from an arithmetic unit in correspondence with a store request transmitted from an instruction processing device, and that is to be written to a cache memory or a memory as a result of the store request, comprising: data storing units of a plurality of hierarchies temporarily holding the store data respectively, and comprised between the store port and the cache memory or the memory; a store data write controlling unit controlling a write of the store data from the store port to the cache memory or the memory via data storing units of one or more hierarchies among the plurality of hierarchies; said data storing units of the plurality of hierarchies respectively comprise a plurality of write buffers; a data write controlling unit controlling a write of the store data from the store port to said data storing unit, and wherein: the store request is divided into a plurality of divided store requests at the store port, and the data storing unit merges the divided store requests transferred from the store port into a merged store request outgoing from the data storing unit; said data storing unit receives the store data from the store port after the instruction processing device commits execution of the store request; said data storing unit including the plurality of write buffers which respectively store the store data received from the store port; said data write controlling unit limits write buffers to being within a range from a write buffer, among the plurality of write buffers, in which data is stored most recently, to a write buffer ahead by n buffers in an order where data is to be stored, when the instruction processing device simultaneously commits execution of a plurality of (n) store requests, and controls a data write to limited write buffers; if a hierarchy in which all of the plurality of write buffers hold data does not exist among the plurality of hierarchies, said store data write controlling unit controls a write of the store data from the store port not via a hierarchy in which all of the plurality of write buffers are empty, but via a write buffer unit in a hierarchy in which a write buffer to which the store data can be written exists; and if hierarchies in which all of the plurality of write buffers hold data exist, said store data write controlling unit controls the write of the store data via a write buffer unit in a hierarchy, from among the hierarchies in which all of the plurality of write buffers hold data, that is closer by one hierarchy than a hierarchy close to the store port.