Configurable IC's with logic resources with offset connections
원문보기
IPC분류정보
국가/구분
United States(US) Patent
등록
국제특허분류(IPC7판)
H03K-019/173
H03K-019/177
G06F-007/38
H01L-025/00
출원번호
US-0082228
(2005-03-15)
등록번호
US-7282950
(2007-10-16)
발명자
/ 주소
Schmit,Herman
Teig,Steven
Hutchings,Brad
Huang,Randy Renfu
출원인 / 주소
Tabula, Inc.
대리인 / 주소
Adeli Law Group PLC
인용정보
피인용 횟수 :
21인용 특허 :
106
초록▼
A configurable integrated circuit ("IC") that includes several configurable tiles arranged in a tile arrangement. Each configurable tile has a set of configurable logic circuits and a set of configurable routing circuits for routing signals between configurable logic circuits. In some embodiments, a
A configurable integrated circuit ("IC") that includes several configurable tiles arranged in a tile arrangement. Each configurable tile has a set of configurable logic circuits and a set of configurable routing circuits for routing signals between configurable logic circuits. In some embodiments, at least a first logic circuit of a first tile has at least one direct connection with a second circuit of a second tile that does not neighbor the first tile and that is not aligned horizontally or vertically with the first tile in the tile arrangement.
대표청구항▼
What is claimed is: 1. A configurable integrated circuit ("IC") comprising: a plurality of configurable tiles arranged in a tile arrangement, each configurable tile having a set of configurable logic circuits and a set of configurable routing circuits for routing signals between configurable logic
What is claimed is: 1. A configurable integrated circuit ("IC") comprising: a plurality of configurable tiles arranged in a tile arrangement, each configurable tile having a set of configurable logic circuits and a set of configurable routing circuits for routing signals between configurable logic circuits; wherein at least a first logic circuit of a first tile has at least one direct connection with a second circuit of a second tile that does not neighbor the first tile and that is not aligned horizontally or vertically with the first tile in the tile arrangement; and wherein said direct connection does not include any intervening interconnect circuits. 2. The configurable IC of claim 1, wherein a plurality of logic circuits of the first tile have at least one direct connection with at least one circuit of another tile that does not neighbor the first tile and that is not aligned horizontally or vertically with the first tile in the tile arrangement. 3. The configurable IC of claim 1, wherein the second circuit is a routing circuit. 4. The configurable IC of claim 3, wherein the second circuit receives output of the first circuit through the direct connection. 5. The configurable IC of claim 1, wherein the second circuit is a logic circuit. 6. The configurable IC of claim 1, wherein the second circuit receives output of the first circuit through the direct connection. 7. The configurable IC of claim 1 further comprising configurable input-select circuits for receiving and selecting inputs for configurable logic circuits, wherein the second circuit is a configurable input-select circuit that through the direct connection receives output of the first logic circuit. 8. The configurable IC of claim 1, wherein each of a plurality of logic circuits of each particular tile in a set of tiles has at least one direct connection with at least one other circuit of another tile that does not neighbor the particular tile and that is not aligned horizontally or vertically with the particular tile in the tile arrangement. 9. The configurable IC of claim 1, wherein the direct connection does not include any intervening circuits. 10. The configurable IC of claim 9, wherein the direct connection includes a set of wire segments and a set of vias. 11. The configurable IC of claim 1, wherein the direct connection includes a set of wire segments and at least one intervening buffer circuit. 12. The configurable IC of claim 1, wherein the plurality of tiles includes at least 300 tiles. 13. The configurable IC of claim 1, wherein the plurality of tiles includes at least 1000 tiles. 14. An electronic device comprising: a configurable integrated circuit ("IC") comprising: a) a plurality of configurable tiles arranged in a tile arrangement, b) each configurable tile having a set of configurable logic circuits and a set of configurable routing circuits for routing signals between configurable logic circuits; c) wherein at least a first logic circuit of a first tile has at least one direct connection with a second circuit of a second tile that does not neighbor the first tile and that is not aligned horizontally or vertically with the first tile in the tile arrangement, and wherein said direct connection does not include any intervening interconnect circuits. 15. The electronic device of claim 14, wherein a plurality of logic circuits of the first tile have at least one direct connection with at least one circuit of another tile that does not neighbor the first tile and that is not aligned horizontally or vertically with the first tile in the tile arrangement. 16. The electronic device of claim 14, wherein the second circuit is a routing circuit. 17. The electronic device of claim 16, wherein the second circuit receives output of the first circuit through the direct connection. 18. The electronic device of claim 14, wherein the second circuit is a logic circuit. 19. The electronic device of claim 14, wherein the second circuit receives output of the first circuit through the direct connection. 20. The electronic device of claim 14 further comprising configurable input-select circuits for receiving and selecting inputs for configurable logic circuits, wherein the second circuit is a configurable input-select circuit that through the direct connection receives output of the first logic circuit. 21. The electronic device of claim 14, wherein each of a plurality of logic circuits of each particular tile in a set of tiles has at least one direct connection with at least one other circuit of another tile that does not neighbor the particular tile and that is not aligned horizontally or vertically with the particular tile in the tile arrangement. 22. A configurable integrated circuit ("IC") comprising: a plurality of configurable tiles arranged in a tile arrangement, each particular tile having a set of configurable logic circuits, a set of configurable routing circuits for routing signals between configurable logic circuits, and a set of configurable input-select circuits for receiving inputs and configurably supplying a sub-set of the received inputs to the configurable logic circuits in the particular tile; wherein at least a first input select circuit of a first tile has at least one direct connection with a second logic circuit of a second tile that does not neighbor the first tile and that is not aligned horizontally or vertically with the first tile in the tile arrangement, wherein the direct connection is for supplying a signal to the first input select circuit, and wherein said direct connection does not include any intervening interconnect circuits. 23. The configurable IC of claim 22, wherein a plurality of input select circuits of the first tile have at least one direct connection with at least one circuit of another tile that does not neighbor the first tile and that is not aligned horizontally or vertically with the first tile in the tile arrangement. 24. The configurable IC of claim 22, wherein the second logic circuit is a look up table. 25. The configurable IC of claim 22, wherein the second logic circuit is a three input logic circuit. 26. The configurable IC of claim 22, wherein each of a plurality of input select circuits of each particular tile in a set of tiles has at least one direct connection with at least one other circuit of another tile that does not neighbor the particular tile and that is not aligned horizontally or vertically with the particular tile in the tile arrangement. 27. The configurable IC of claim 22, wherein the plurality of tiles includes at least 300 tiles. 28. The configurable IC of claim 22, wherein the plurality of tiles includes at least 1000 tiles. 29. An electronic device comprising: a configurable integrated circuit ("IC") comprising: a plurality of configurable tiles arranged in a tile arrangement, each particular tile having a set of configurable logic circuits, a set of configurable routing circuits for routing signals between configurable logic circuits, and a set of configurable input-select circuits for receiving inputs and configurably supplying a sub-set of the received inputs to the configurable logic circuits in the particular tile; wherein at least a first input select circuit of a first tile has at least one direct connection with a second logic circuit of a second tile that does not neighbor the first tile and that is not aligned horizontally or vertically with the first tile in the tile arrangement, wherein the direct connection is for supplying a signal to the first input select circuit, and wherein said direct connection does not include any intervening interconnect circuits. 30. The electronic device of claim 29, wherein a plurality of input select circuits of the first tile have at least one direct connection with at least one circuit of another tile that does not neighbor the first tile and that is not aligned horizontally or vertically with the first tile in the tile arrangement. 31. The electronic device of claim 29, wherein the second logic circuit is a look up table. 32. The electronic device of claim 29, wherein the second logic circuit is a three input logic circuit. 33. The electronic device of claim 29, wherein each of a plurality of input select circuits of each particular tile in a set of tiles has at least one direct connection with at least one other circuit of another tile that does not neighbor the particular tile and that is not aligned horizontally or vertically with the particular tile in the tile arrangement.
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이 특허에 인용된 특허 (106)
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