초록 ▼

A high speed bus system in which at least one master device, such as a processor and at least one DRAM slave device are coupled to the bus. An innovative packet format and device interface which utilizes a plurality of time and space saving features in order to decrease the die size of the device re

A high speed bus system in which at least one master device, such as a processor and at least one DRAM slave device are coupled to the bus. An innovative packet format and device interface which utilizes a plurality of time and space saving features in order to decrease the die size of the device receiver and decrease the overall latency on the bus is provided. In the preferred embodiment the request packet is transmitted on ten multiplexed transmission lines, identified as BusCtl and BusData [8:0]. The packet is transmitted over six sequential bus cycles, wherein during each bus cycle, a different portion of the packet is transmitted. The lower order address bits are moved ahead of the higher order address bits of the memory request. This enables the receiving device to process the memory request faster as the locality of the memory reference with respect to previous references can be immediately determined and page mode accesses on the DRAM can be initiated as quickly as possible. The type of memory access is arranged over a plurality of clock cycles, placing the more critical bits first. The count of blocks of data requested is arranged to minimize the number of bit positions in the packet used and therefore the number of transmission lines of the bus and the number of bus receiver contacts on the receiving device.

대표청구항 ▼

What is claimed is: 1. A method of transmitting digital information, comprising the steps of: (a) transmitting a first word of a packet, comprising the steps of: (1) transmitting start information onto a id="DEL-S-00001" date="20071009" firstid="DEL-S-00001" bus, wherein the start information indi

What is claimed is: 1. A method of transmitting digital information, comprising the steps of: (a) transmitting a first word of a packet, comprising the steps of: (1) transmitting start information onto a id="DEL-S-00001" date="20071009" firstid="DEL-S-00001" bus, wherein the start information indicates a start of the packet; (2) transmitting lower order memory address bits onto a id="DEL-S-00002" date="20071009" firstid="DEL-S-00002" group of id="DEL-S-00003" date="20071009" secondid="DEL-S-00003" bus lines id="INS-S-00001" date="20071009" of the busid="INS-S-00001" ; id="INS-S-00002" date="20071009" and id="INS-S-00002" (3) transmitting first op code information onto id="DEL-S-00004" date="20071009" an Nthid="DEL-S-00004" id="INS-S-00003" date="20071009" a first id="INS-S-00003" bus line of the id="DEL-S-00005" date="20071009" secondid="DEL-S-00005" bus id="DEL-S-00006" date="20071009" lines, wherein N is an integer, andid="DEL-S-00006" wherein the id="DEL-S-00007" date="20071009" Nthid="DEL-S-00007" id="INS-S-00004" date="20071009" first id="INS-S-00004" bus line is not a bus line within the id="DEL-S-00008" date="20071009" firstid="DEL-S-00008" group of id="DEL-S-00009" date="20071009" the secondid="DEL-S-00009" bus lines; id="INS-S-00005" date="20071009" and id="INS-S-00005" (b) transmitting a second word of the packet, comprising the steps of: (1) transmitting second op code id="INS-S-00006" date="20071009" information id="INS-S-00006" onto the id="DEL-S-00010" date="20071009" firstid="DEL-S-00010" bus; (2) transmitting higher order memory address bits onto the id="DEL-S-00011" date="20071009" firstid="DEL-S-00011" group of id="DEL-S-00012" date="20071009" the secondid="DEL-S-00012" bus lines; id="INS-S-00007" date="20071009" and id="INS-S-00007" (3) transmitting third op code information onto the id="DEL-S-00013" date="20071009" Nthid="DEL-S-00013" id="INS-S-00008" date="20071009" first id="INS-S-00008" bus line id="DEL-S-00014" date="20071009" of the second bus linesid="DEL-S-00014" . 2. The method of claim 1 of transmitting digital information, further comprising the steps of: (a) transmitting a third word of id="DEL-S-00015" date="20071009" aid="DEL-S-00015" id="INS-S-00009" date="20071009" the id="INS-S-00009" packet, comprising the steps of: (1) transmitting a master device code for detecting collisions; (2) transmitting count information for determining a count of a number of bytes of a memory transaction. 3. In a digital system comprising a master device and at least one memory device, a process for transmitting memory requests to the memory device comprising the steps of: transmitting a first word of a packet, comprising the steps of: transmitting start information onto a id="DEL-S-00016" date="20071009" firstid="DEL-S-00016" bus id="DEL-S-00017" date="20071009" lineid="DEL-S-00017" , said start information indicating the start of the packetid="DEL-S-00018" date="20071009" ,id="DEL-S-00018" id="INS-S-00010" date="20071009" ;id="INS-S-00010" transmitting a first portion of a lower order memory address bits onto a id="DEL-S-00019" date="20071009" firstid="DEL-S-00019" group of id="DEL-S-00020" date="20071009" secondid="DEL-S-00020" bus lines id="INS-S-00011" date="20071009" of the busid="INS-S-00011" , said lower order memory bits comprising information to perform page mode memory accessesid="DEL-S-00021" date="20071009" ,id="DEL-S-00021" id="INS-S-00012" date="20071009" ; id="INS-S-00012" and transmitting a first portion of op code information onto id="DEL-S-00022" date="20071009" a second groupid="DEL-S-00022" id="INS-S-00013" date="20071009" at least a first bus line id="INS-S-00013" of the id="DEL-S-00023" date="20071009" secondid="DEL-S-00023" id="INS-S-00014" date="20071009" group of id="INS-S-00014" bus lines; and transmitting a second word of the packet, comprising the steps of: transmitting a second portion of op code information onto the first bus lineid="DEL-S-00024" date="20071009" ,id="DEL-S-00024" id="INS-S-00015" date="20071009" ;id="INS-S-00015" transmitting a third portion of op code information onto the id="DEL-S-00025" date="20071009" second groupid="DEL-S-00025" id="INS-S-00016" date="20071009" at least a first bus line id="INS-S-00016" of the id="DEL-S-00026" date="20071009" secondid="DEL-S-00026" id="INS-S-00017" date="20071009" group of id="INS-S-00017" bus lines, wherein an op code for page mode accesses can be detected from said first, second and third portions of op code information; and transmitting a second portion of the lower order memory address bits onto the id="DEL-S-00027" date="20071009" firstid="DEL-S-00027" group of id="DEL-S-00028" date="20071009" the secondid="DEL-S-00028" bus lines; wherein page mode access can be performed after transmission of the second word of the packet. 4. In a computer system comprising a master device and at least one memory device, a bus system for transmitting memory requests to the memory device comprising: a plurality of bus lines for transmission of memory requests; a packet comprising a memory request for transmission across the id="INS-S-00018" date="20071009" plurality of id="INS-S-00018" bus lines, said packet comprising: a first word comprising: start information indicating the start of the packet; a first portion of lower order memory address bits comprising information to perform page mode memory accesses; and a first portion of op code information; and a second word comprising: a second and id="INS-S-00019" date="20071009" a id="INS-S-00019" third portion of op code information, wherein an op code for page mode accesses can be detected from the first, second and third portions of op code information, and a second portion of id="DEL-S-00029" date="20071009" theid="DEL-S-00029" lower order memory address bits; wherein page mode access can be performed after transmission of the second word of the packet. 5. The bus system as set forth in claim 4 wherein said start information is located at a predetermined location in the first word of the packet, said system further comprising: means for monitoring id="DEL-S-00030" date="20071009" theid="DEL-S-00030" id="INS-S-00020" date="20071009" a id="INS-S-00020" predetermined location in each word id="INS-S-00021" date="20071009" of the packet id="INS-S-00021" during transmission of id="DEL-S-00031" date="20071009" subsequentid="DEL-S-00031" id="INS-S-00022" date="20071009" the id="INS-S-00022" words of the packet id="INS-S-00023" date="20071009" that are subsequent to the first and second words id="INS-S-00023" for information other than the start id="DEL-S-00032" date="20071009" of the packetid="DEL-S-00032" id="INS-S-00024" date="20071009" informationid="INS-S-00024" ; and means for detecting a collision if information occurs at the predetermined location in id="DEL-S-00033" date="20071009" subsequentid="DEL-S-00033" words of the packet id="INS-S-00025" date="20071009" that are subsequent to the first and second wordsid="INS-S-00025" , said information occurring due to id="DEL-S-00034" date="20071009" theid="DEL-S-00034" start information of id="DEL-S-00035" date="20071009" a secondid="DEL-S-00035" id="INS-S-00026" date="20071009" another id="INS-S-00026" packet overlapping the id="DEL-S-00036" date="20071009" firstid="DEL-S-00036" packet. 6. The bus system as forth in claim 5, wherein said packet further comprises a code identifying id="DEL-S-00037" date="20071009" theid="DEL-S-00037" id="INS-S-00027" date="20071009" a id="INS-S-00027" device transmitting the packet, said means for detecting a collision further comprising means for detecting the code to determine id="DEL-S-00038" date="20071009" whereid="DEL-S-00038" id="INS-S-00028" date="20071009" whether id="INS-S-00028" the code is valid, an invalid code resulting from a collision id="DEL-S-00039" date="20071009" of packetsid="DEL-S-00039" id="INS-S-00029" date="20071009" between the packet and another packetid="INS-S-00029" . 7. The bus system as set forth in claim 4, wherein said packet further comprises count information indicating the number of bytes of id="DEL-S-00040" date="20071009" memoryid="DEL-S-00040" id="INS-S-00030" date="20071009" data id="INS-S-00030" to be transmitted across the bus lines during id="DEL-S-00041" date="20071009" the memoryid="DEL-S-00041" id="INS-S-00031" date="20071009" a id="INS-S-00031" transaction id="DEL-S-00042" date="20071009" requestedid="DEL-S-00042" id="INS-S-00032" date="20071009" corresponding to the memory requestid="INS-S-00032" . 8. The bus system as set forth in claim 7, wherein said data is transmitted in a id="INS-S-00033" date="20071009" plurality of id="INS-S-00033" multiple byte id="DEL-S-00043" date="20071009" block formatid="DEL-S-00043" id="INS-S-00034" date="20071009" blocksid="INS-S-00034" , said system further comprising: means for generating a first mask for id="DEL-S-00044" date="20071009" theid="DEL-S-00044" id="INS-S-00035" date="20071009" data in a id="INS-S-00035" first multiple byte block of the id="DEL-S-00045" date="20071009" data to be transmittedid="DEL-S-00045" id="INS-S-00036" date="20071009" plurality of multiple byte blocksid="INS-S-00036" , said id="INS-S-00037" date="20071009" first id="INS-S-00037" mask indicating id="DEL-S-00046" date="20071009" theid="DEL-S-00046" id="INS-S-00038" date="20071009" which id="INS-S-00038" bytes of the id="INS-S-00039" date="20071009" first id="INS-S-00039" multiple byte block id="DEL-S-00047" date="20071009" whichid="DEL-S-00047" are part of the id="DEL-S-00048" date="20071009" memory operation requestedid="DEL-S-00048" id="INS-S-00040" date="20071009" transactionid="INS-S-00040" ; and means for generating a second mask for id="DEL-S-00049" date="20071009" theid="DEL-S-00049" id="INS-S-00041" date="20071009" data in a id="INS-S-00041" last multiple byte block id="INS-S-00042" date="20071009" of the plurality of multiple byte blocksid="INS-S-00042" , said id="INS-S-00043" date="20071009" second id="INS-S-00043" mask indicating id="DEL-S-00050" date="20071009" theid="DEL-S-00050" id="INS-S-00044" date="20071009" which id="INS-S-00044" bytes of the last multiple byte block id="DEL-S-00051" date="20071009" whichid="DEL-S-00051" are part of the id="DEL-S-00052" date="20071009" memory operation requestedid="DEL-S-00052" id="INS-S-00045" date="20071009" transactionid="INS-S-00045" . 9. The bus system as set forth in claim 8, wherein id="DEL-S-00053" date="20071009" dataid="DEL-S-00053" id="INS-S-00046" date="20071009" each multiple byte block of the plurality of multiple byte blocks id="INS-S-00046" is transmitted in 4 byte blocks, the first mask is generated from id="DEL-S-00054" date="20071009" theid="DEL-S-00054" two least significant bits of the id="INS-S-00047" date="20071009" lower order memory id="INS-S-00047" address bits and the second mask is generated from id="DEL-S-00055" date="20071009" theid="DEL-S-00055" two least significant bits of the count information. 10. The bus system as set forth in claim 8, further comprising a first and second look up table id="INS-S-00048" date="20071009" each id="INS-S-00048" comprising mask patterns, said id="INS-S-00049" date="20071009" first and second id="INS-S-00049" masks id="INS-S-00050" date="20071009" being id="INS-S-00050" generated by performing a table lookup id="INS-S-00051" date="20071009" of the first and second look up tables id="INS-S-00051" respectively using the address bits and the count information. 11. The bus system as set forth in claim 4, further comprising a summing means for summing id="DEL-S-00056" date="20071009" theid="DEL-S-00056" two least significant address bits and id="INS-S-00052" date="20071009" an id="INS-S-00052" internal byte count to produce id="DEL-S-00057" date="20071009" anid="DEL-S-00057" overflow id="DEL-S-00058" date="20071009" valueid="DEL-S-00058" id="INS-S-00053" date="20071009" information id="INS-S-00053" and count information, said overflow information indicating id="DEL-S-00059" date="20071009" thatid="DEL-S-00059" although id="DEL-S-00060" date="20071009" the sizeid="DEL-S-00060" id="INS-S-00054" date="20071009" an amount id="INS-S-00054" of id="DEL-S-00061" date="20071009" theid="DEL-S-00061" data id="DEL-S-00062" date="20071009" ofid="DEL-S-00062" id="INS-S-00055" date="20071009" corresponding to id="INS-S-00055" the memory request is less than the maximum number of bytes allowed in id="DEL-S-00063" date="20071009" theid="DEL-S-00063" id="INS-S-00056" date="20071009" a id="INS-S-00056" memory operation id="INS-S-00057" date="20071009" corresponding to the memory requestid="INS-S-00057" , id="DEL-S-00064" date="20071009" theid="DEL-S-00064" granularity of id="DEL-S-00065" date="20071009" theid="DEL-S-00065" id="INS-S-00058" date="20071009" a id="INS-S-00058" multiple byte block format transmitted id="DEL-S-00066" date="20071009" acresid="DEL-S-00066" id="INS-S-00059" date="20071009" across id="INS-S-00059" the id="INS-S-00060" date="20071009" plurality of id="INS-S-00060" bus id="INS-S-00061" date="20071009" lines id="INS-S-00061" prohibits id="DEL-S-00067" date="20071009" theid="DEL-S-00067" id="INS-S-00062" date="20071009" a id="INS-S-00062" transaction, and, the id="INS-S-00063" date="20071009" memory id="INS-S-00063" request id="DEL-S-00068" date="20071009" should beid="DEL-S-00068" id="INS-S-00064" date="20071009" is id="INS-S-00064" separated into two separate memory requests. id="INS-S-00065" date="20071009" 12. A method of operation in a memory device, the memory device having an array of memory cells, the method comprising: receiving first operation code information during a first clock cycle of an external clock signal; receiving second operation code information successively after receiving the first operation code information; receiving a first column address, the first column address representing a column locality of a first storage location within a first row in the array; receiving a first row address successively after receiving the first column address, the first row address representing a location of the first row in the array; and accessing a first memory cell of the array of memory cells, the first memory cell being located at the first storage location, wherein data stored in the first memory cell is accessed for a memory operation based at least in part on the first and second operation code information.id="INS-S-00065" id="INS-S-00066" date="20071009" 13. The method of claim 12 further comprising: receiving a second column address and page mode control information, the second column address representing a column locality of a second storage location within the first row in the array; and accessing a second memory cell of the array of memory cells, the second memory cell being located at the second storage location.id="INS-S-00066" id="INS-S-00067" date="20071009" 14. The method of claim 13 further comprising receiving a second row address in succession to receiving the second column address, the second row address representing the location of the first row in the array.id="INS-S-00067" id="INS-S-00068" date="20071009" 15. The method of claim 13 wherein the first column address and the first row address are both included in a first packet, and the second column address and the page mode information are included in a second packet.id="INS-S-00068" id="INS-S-00069" date="20071009" 16. The method of claim 12 wherein the first column address is received in a first portion of a packet and the first row address is received in a second portion of the packet.id="INS-S-00069" id="INS-S-00070" date="20071009" 17. The method of claim 16 wherein the packet further includes start information representing the beginning of the packet.id="INS-S-00070" id="INS-S-00071" date="20071009" 18. The method of claim 12 further comprising receiving block size information, the block size information representing an amount of data to be output by the memory device.id="INS-S-00071" id="INS-S-00072" date="20071009" 19. The method of claim 12 wherein the first column address is received during the first clock cycle and the first row address is received during a second clock cycle.id="INS-S-00072" id="INS-S-00073" date="20071009" 20. The method of claim 19 wherein a first portion of the first column address is received during a first bus cycle and a second portion of the first column address is received during a second bus cycle, and wherein both the first and second bus cycles transpire during the first clock cycle.id="INS-S-00073" id="INS-S-00074" date="20071009" 21. The method of claim 12 further comprising receiving page mode access information.id="INS-S-00074" id="INS-S-00075" date="20071009" 22. The method of claim 21 wherein the page mode access information is received concurrently with the first column address.id="INS-S-00075" id="INS-S-00076" date="20071009" 23. The method of claim 21 wherein the page mode access information includes a code wherein: in a first state of the code, the memory device is operable in a page mode; and in a second state of the code, the memory device is operable in a normal mode.id="INS-S-00076" id="INS-S-00077" date="20071009" 24. The method of claim 21 wherein the page mode access information includes a first portion and a second portion, wherein the first portion is received concurrently with the first column address, and the second portion is received concurrently with the first row address.id="INS-S-00077" id="INS-S-00078" date="20071009" 25. The method of claim 24 wherein the first portion of the page mode access information and the first column address are both included in a first portion of a packet, and wherein the second portion of the page mode access information and the first row address are both included in a second portion of the packet.id="INS-S-00078" id="INS-S-00079" date="20071009" 26. A method of controlling a memory device, the memory device having an array of memory cells, the method comprising: issuing first operation code information during a first clock cycle of an external clock signal; issuing second operation code information following the issuance of the first operation code information; issuing a first column address to the memory device, the first column address representing a column locality of a first storage location within a first row in the array; and issuing a first row address following the issuance of the first column address, the first row address representing a location of the first row in the array, wherein data stored in a memory cell located at the location is accessed for a memory operation based at least in part on the first and second operation code information.id="INS-S-00079" id="INS-S-00080" date="20071009" 27. The method of claim 26 further comprising issuing a second column address and page mode control information, the second column address representing a column locality of a second storage location within the first row in the array.id="INS-S-00080" id="INS-S-00081" date="20071009" 28. The method of claim 27 further comprising issuing a second row address following the issuance of the second column address, the second row address representing the location of the first row in the array.id="INS-S-00081" id="INS-S-00082" date="20071009" 29. The method of claim 28 wherein the first column address and the first row address are both included in a first packet, and the second column address and the page mode information are included in a second packet.id="INS-S-00082" id="INS-S-00083" date="20071009" 30. The method of claim 26 wherein the first column address is issued in a first portion of a packet and the first row address is issued in a second portion of the packet.id="INS-S-00083" id="INS-S-00084" date="20071009" 31. The method of claim 30 wherein the packet further includes start information representing the beginning of the packet.id="INS-S-00084" id="INS-S-00085" date="20071009" 32. The method of claim 26 further comprising providing block size information, the block size information representing an amount of data to be output by the memory device.id="INS-S-00085" id="INS-S-00086" date="20071009" 33. The method of claim 32 wherein the first column address, the first row address and the block size information are included in a packet.id="INS-S-00086" id="INS-S-00087" date="20071009" 34. The method of claim 33 wherein the first column address, the first row address and the block size information are included in the same packet.id="INS-S-00087" id="INS-S-00088" date="20071009" 35. The method of claim 26 wherein the first column address is issued during the first clock cycle, and the first row address is issued during a second clock cycle.id="INS-S-00088" id="INS-S-00089" date="20071009" 36. The method of claim 35 wherein a first portion of the first column address is issued during a first bus cycle and a second portion of the first column address is issued during a second bus cycle, and wherein both the first and second bus cycles transpire during the first clock cycle.id="INS-S-00089" id="INS-S-00090" date="20071009" 37. The method of claim 26 further comprising providing page mode access information.id="INS-S-00090" id="INS-S-00091" date="20071009" 38. The method of claim 37 wherein the page mode access information is provided concurrently with the issuance of the first column address.id="INS-S-00091" id="INS-S-00092" date="20071009" 39. The method of claim 37 wherein the page mode access information includes a code wherein: when the code is in a first state, the memory device operates in a page mode; and when the code is in a second state, the memory device operates in a normal mode.id="INS-S-00092" id="INS-S-00093" date="20071009" 40. The method of claim 37 wherein the page mode access information includes a first portion and a second portion, wherein the first portion is provided concurrently with the issuance of the first column address, and the second portion is provided concurrently with the issuance of the first row address.id="INS-S-00093" id="INS-S-00094" date="20071009" 41. The method of claim 40 wherein the first portion of the page mode access information and the first column address are both included in a first word of a packet, and wherein the second portion of the page mode access information and the first row address are both included in a second word of a packet.id="INS-S-00094"