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Solder ball pad structure 원문보기

IPC분류정보
국가/구분 United States(US) Patent 등록
국제특허분류(IPC7판)
  • H01L-029/40
출원번호 US-0750059 (2003-12-30)
등록번호 US-7294929 (2007-11-13)
발명자 / 주소
  • Miyazaki,Hiroshi
출원인 / 주소
  • Texas Instruments Incorporated
인용정보 피인용 횟수 : 72  인용 특허 : 30

초록

An interconnect structure a substrate, a contact pad disposed over a surface of the substrate, and an insulative mask disposed over the contact pad. The insulative mask can include an opening that is aligned over and exposes an inner portion of the contact pad. The inner portion of the contact pad i

대표청구항

What is claimed is: 1. An interconnect structure comprising: a substrate; a conductive contact pad having a first elastic modulus, disposed over a portion of the substrate surface, having an inner portion and an outer portion surrounding the inner portion; a compliant layer having a second elastic

이 특허에 인용된 특허 (30)

  1. Mei Sheng Zhou SG; Sangki Hong SG; Simon Chooi SG, Aluminum and copper bimetallic bond pad scheme for copper damascene interconnects.
  2. Lutz, Michael A., Apparatus with compliant electrical terminals, and methods for forming same.
  3. Matsuda Tatsuharu (Kawasaki JPX) Minamizawa Masaharu (Kawasaki JPX), Bump electrode, semiconductor integrated circuit device using the same, multi-chip module having the semiconductor integ.
  4. Kwon Oh-Kyong (Richardson TX) Malhi Satwinder (Garland TX) Hashimoto Masahi (Garland TX), Compliant contact pad.
  5. Nolan Ernest R. (Round Rock TX) Duane Diana C. (Cedar Park TX) Herder Todd H. (Corvallis OR) Bishop Thomas A. (Austin TX) Tran Kimcuc T. (Austin TX) Froehlich Robert W. (Austin TX) German Randy L. (A, Compliant electrically connective bumps for an adhesive flip chip integrated circuit device and methods for forming same.
  6. Alcoe, David J., Compliant laminate connector.
  7. Joseph Fjelstad ; Konstantine Karavakis, Compliant microelectronic assemblies.
  8. Solberg Vernon, Compliant multichip package.
  9. Yaniv, Zvi; Kumar, Nalin; Potter, Nathan, Display panel test device.
  10. Joseph Fjelstad, Expandable interposer for a microelectronic package and method therefor.
  11. Wojnarowski Robert John ; Gorczyca Thomas Bent ; Weaver ; Jr. Stanton Earl, High density interconnected circuit module with a compliant layer as part of a stress-reducing molded substrate.
  12. Fjelstad, Joseph; Karavakis, Konstantine, Image forming apparatus with improved transfer efficiency.
  13. Darveaux Robert F. ; Miles Barry M. ; Copia Alexander W., Making solder ball mounting pads on substrates.
  14. Munroe Robert A. ; Greer Stuart E., Method for forming interconnect bumps on a semiconductor die.
  15. Inoue, Kosuke; Tenmei, Hiroyuki; Yamaguchi, Yoshihide; Oroku, Noriyuki; Hozoji, Hiroshi; Tsunoda, Shigeharu; Minagawa, Madoka; Kanda, Naoya; Anjo, Ichiro; Nishimura, Asao; Yajima, Akira; Ujiie, Kenji, Method for producing a semiconductor device.
  16. Brintzinger, Axel; Uhlendorf, Ingo; Schenk, Andre; Wollanke, Alexander, Method for the solder-stop structuring of elevations on wafers.
  17. Robl, Werner; Goebel, Thomas; Brintzinger, Axel Christoph; Friese, Gerald, Method of eliminating back-end rerouting in ball grid array packaging.
  18. Paul Hoffman, Microelectronic device package having a heat sink structure for increasing the thermal conductivity of the package.
  19. Pritchett, Samuel D.; Coyle, Anthony L.; Buschbom, Milton L., Plastic chip-scale package having integrated passive components.
  20. Khandros Igor Y. (Peekskill NY) DiStefano Thomas H. (Bronxville NY), Semiconductor chip assemblies having interposer and flexible lead.
  21. Fjelstad Joseph ; Karavakis Konstantine, Semiconductor chip package with fan-in leads.
  22. Inoue, Kosuke; Tenmei, Hiroyuki; Yamaguchi, Yoshihide; Oroku, Noriyuki; Hozoji, Hiroshi; Tsunoda, Shigeharu; Minagawa, Madoka; Kanda, Naoya; Anjo, Ichiro; Nishimura, Asao; Yajima, Akira; Ujiie, Kenji, Semiconductor device and method for manufacturing the same.
  23. Glenn Thomas P. ; Hollaway Roy D.,PHX ; Panczak Anthony E., Solder ball joint.
  24. Lee, Jin-Yuan; Lin, Eric, Thermal compliant semiconductor chip wiring structure for chip scale packaging.
  25. Kim, Gu-Sung; Jang, Dong-Hyeon; Son, Min-Young; Kang, Sa-Yoon, Wafer level package and method for manufacturing the same.
  26. Lo, Wei-Chung; Huang, Hsin-Chien; Lu, Ming, Wafer level package incorporating dual compliant layers and method for fabrication.
  27. Enboa Wu TW; Tsung-Yao Chu TW; Hsin-Chien Huang TW; Chung-Tao Chang TW, Wafer level package incorporating dual stress buffer layers for I/O redistribution and method for fabrication.
  28. Kung Ling-Chen,TWX ; Lin Jyh-Rong,TWX ; Chen Kuo-Chuan,TWX, Wafer level packaging method and packages formed.
  29. Palagonia Anthony Michael, Wafer with elevated contact structures.
  30. Bhansali Ameet S. ; Samuelson Gay M. ; Murali Venkatesan ; Gasparek Michael J. ; Chen Shou H. ; Mencinger Nicholas P. ; Lee Ching C.,MYX ; Jeng Kevin, Wire bonding surface and bonding method.

이 특허를 인용한 특허 (72)

  1. Choudhury, Debabani; Alluri, Prasad, Apparatus and method for embedding components in small-form-factor, system-on-packages.
  2. Choudhury, Debabani; Alluri, Prasad, Apparatus and method for embedding components in small-form-factor, system-on-packages.
  3. Daubenspeck, Timothy H.; Gambino, Jeffrey P.; Muzzy, Christopher D.; Sauter, Wolfgang; Sullivan, Timothy D., Buffer pad in solder bump connections and methods of manufacture.
  4. Pendse, Rajendra D., Bump-on-lead flip chip interconnection.
  5. Pendse, Rajendra D., Bump-on-lead flip chip interconnection.
  6. Pendse, Rajendra D., Bump-on-lead flip chip interconnection.
  7. Pendse, Rajendra D., Bump-on-lead flip chip interconnection.
  8. Pendse, Rajendra D., Bump-on-lead flip chip interconnection.
  9. Pendse, Rajendra D., Bump-on-lead flip chip interconnection.
  10. Kuroda, Nobuhisa; Kubota, Naoki, Circuit board and manufacturing method thereof.
  11. Pendse, Rajendra D.; Kim, Youngcheol; Lee, TaeKeun; Na, GuiChea; Kim, GwangJin, Filp chip interconnection structure with bump on partial pad and method thereof.
  12. Pendse, Rajendra D., Flip chip interconnect solder mask.
  13. Pendse, Rajendra D., Flip chip interconnect solder mask.
  14. Pendse, Rajendra D., Flip chip interconnect solder mask.
  15. Pendse, Rajendra D., Flip chip interconnection having narrow interconnection sites on the substrate.
  16. Pendse, Rajendra D., Flip chip interconnection having narrow interconnection sites on the substrate.
  17. Pendse, Rajendra D., Flip chip interconnection pad layout.
  18. Kim, Oh Han; Kim, Kyung Moon, Flip chip interconnection system having solder position control mechanism.
  19. Pendse, Rajendra D., Fusible I/O interconnection systems and methods for flip-chip packaging involving substrate-mounted stud bumps.
  20. Pendse, Rajendra D., Fusible I/O interconnection systems and methods for flip-chip packaging involving substrate-mounted stud bumps.
  21. Kim, KyungOe; Choi, Haengcheol; Kim, Kyung Moon; Pendse, Rajendra D., Integrated circuit mount system with solder mask pad.
  22. Yang, Chih-Kuang, Metal structure of flexible multi-layer substrate and manufacturing method thereof.
  23. Tay, Cheng Siew; Cheng, Swee Kian; Goh, Eng Huat, Method and apparatus for reducing electrical interconnection fatigue.
  24. Kawai, Satoru; Sakai, Kenji; Chen, Liyi, Method for manufacturing a printed wiring board.
  25. Pendse, Rajendra D., Method of forming a bump-on-lead flip chip interconnection having higher escape routing density.
  26. Jang, KiYoun; Kim, SungSoo; Kang, YongHee, Method of forming vertically offset bond on trace interconnects on recessed and raised bond fingers.
  27. Kawai, Satoru; Sakai, Kenji; Chen, Liyi, Printed wiring board and method for manufacturing printed wiring board.
  28. Pendse, Rajendra D., Semiconductor device and method of confining conductive bump material during reflow with solder mask patch.
  29. Pendse, Rajendra D., Semiconductor device and method of confining conductive bump material during reflow with solder mask patch.
  30. Pendse, Rajendra D., Semiconductor device and method of confining conductive bump material during reflow with solder mask patch.
  31. Pendse, Rajendra D., Semiconductor device and method of confining conductive bump material during reflow with solder mask patch.
  32. Pendse, Rajendra D., Semiconductor device and method of confining conductive bump material with solder mask patch.
  33. Pendse, Rajendra D., Semiconductor device and method of confining conductive bump material with solder mask patch.
  34. Pagaila, Reza A.; Pendse, Rajendra D.; Koo, Jun Mo, Semiconductor device and method of forming bond-on-lead interconnection for mounting semiconductor die in FO-WLCSP.
  35. Pagaila, Reza A.; Pendse, Rajendra D.; Koo, Jun Mo, Semiconductor device and method of forming bond-on-lead interconnection for mounting semiconductor die in Fo-WLCSP.
  36. Pendse, Rajendra D., Semiconductor device and method of forming bump-on-lead interconnection.
  37. Pendse, Rajendra D., Semiconductor device and method of forming bump-on-lead interconnection.
  38. Pendse, Rajendra D., Semiconductor device and method of forming bump-on-lead interconnection.
  39. Pendse, Rajendra D., Semiconductor device and method of forming composite bump-on-lead interconnection.
  40. Pendse, Rajendra D., Semiconductor device and method of forming composite bump-on-lead interconnection.
  41. Pendse, Rajendra D., Semiconductor device and method of forming composite bump-on-lead interconnection.
  42. Pendse, Rajendra D., Semiconductor device and method of forming electrical interconnect with stress relief void.
  43. Pendse, Rajendra D., Semiconductor device and method of forming flipchip interconnection structure with bump on partial pad.
  44. Pendse, Rajendra D., Semiconductor device and method of forming high routing density BOL BONL and BONP interconnect sites on substrate.
  45. Shim, Seong Bo; Kim, Kyung Oe; Kang, Yong Hee, Semiconductor device and method of forming insulating layer on conductive traces for electrical isolation in fine pitch bonding.
  46. Shim, Seong Bo; Kim, Kyung Oe; Kang, Yong Hee, Semiconductor device and method of forming insulating layer on conductive traces for electrical isolation in fine pitch bonding.
  47. Pendse, Rajendra D., Semiconductor device and method of forming narrow interconnect sites on substrate with elongated mask openings.
  48. Pendse, Rajendra D., Semiconductor device and method of forming pad layout for flipchip semiconductor die.
  49. Pendse, Rajendra D., Semiconductor device and method of forming vertical interconnect structure between semiconductor die and substrate.
  50. Pagaila, Reza A.; Jang, KiYoun; Lee, HunTeak, Semiconductor device and method of forming vertically offset bond on trace interconnect structure on leadframe.
  51. Pagaila, Reza A.; Jang, KiYoun; Lee, HunTeak, Semiconductor device and method of forming vertically offset bond on trace interconnect structure on leadframe.
  52. Pagaila, Reza A.; Jang, KiYoun; Lee, HunTeak, Semiconductor device and method of forming vertically offset bond on trace interconnects on different height traces.
  53. Cho, SungWon; Jang, KiYoun; Kang, YongHee; Park, Hyung Sang, Semiconductor device and method of forming vertically offset conductive pillars over first substrate aligned to vertically offset BOT interconnect sites formed over second substrate.
  54. Cho, SungWon; Jang, KiYoun; Kang, YongHee; Park, Hyung Sang, Semiconductor device and method of forming vertically offset conductive pillars over first substrate aligned to vertically offset BOT interconnect sites formed over second substrate.
  55. Pendse, Rajendra D., Semiconductor device and method of self-confinement of conductive bump material during reflow without solder mask.
  56. Pendse, Rajendra D., Semiconductor device and method of self-confinement of conductive bump material during reflow without solder mask.
  57. Pendse, Rajendra D., Semiconductor device and method of self-confinement of conductive bump material during reflow without solder mask.
  58. Pendse, Rajendra D., Semiconductor device and method of self-confinement of conductive bump material during reflow without solder mask.
  59. Pendse, Rajendra D., Semiconductor device and method of self-confinement of conductive bump material during reflow without solder mask.
  60. Pendse, Rajendra D., Semiconductor device and method of self-confinement of conductive bump material during reflow without solder mask.
  61. Jang, KiYoun; Kim, SungSoo; Kang, YongHee, Semiconductor device having vertically offset bond on trace interconnects on recessed and raised bond fingers.
  62. Jang, KiYoun; Kim, SungSoo; Kang, YongHee, Semiconductor device having vertically offset bond on trace interconnects on recessed and raised bond fingers.
  63. Guerin, Luc; Interrante, Mario J.; Shapiro, Michael J.; Tran-Quinn, Thuy; Truong, Van T., Solder ball contact susceptible to lower stress.
  64. Guerin, Luc; Interrante, Mario J.; Shapiro, Michael J.; Tran-Quinn, Thuy; Truong, Van T., Solder ball contact susceptible to lower stress.
  65. Pendse, Rajendra D.; Kim, KyungOe; Kang, TaeWoo, Solder joint flip chip interconnection.
  66. Pendse, Rajendra D.; Kim, KyungOe; Kang, TaeWoo, Solder joint flip chip interconnection.
  67. Pendse, Rajendra D.; Kim, KyungOe; Kang, TaeWoo, Solder joint flip chip interconnection.
  68. Pendse, Rajendra D.; Kim, KyungOe; Kang, TaeWoo, Solder joint flip chip interconnection.
  69. Pendse, Rajendra D.; Kim, KyungOe; Kang, TaeWoo, Solder joint flip chip interconnection having relief structure.
  70. Pendse, Rajendra D.; Kim, KyungOe; Kang, TaeWoo, Solder joint flip chip interconnection having relief structure.
  71. Pendse, Rajendra D.; Kim, KyungOe; Kang, TaeWoo, Solder joint flip chip interconnection having relief structure.
  72. Pendse, Rajendra D.; Kim, KyungOe; Kang, TaeWoo, Solder joint flip chip interconnection having relief structure.
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