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A field programmable gate array includes a virtual bus interface that receives a control word from a host processor over a standard I/O bus. A configurable very long instruction word (VLIW) controller receives the control word via virtual bus interface signals mapped from the virtual bus interface.

A field programmable gate array includes a virtual bus interface that receives a control word from a host processor over a standard I/O bus. A configurable very long instruction word (VLIW) controller receives the control word via virtual bus interface signals mapped from the virtual bus interface. A reconfigurable communication and control fabric controls the data paths and programming modes of single instruction-multiple data (SIMD) processing element cells. The configurable VLIW controller has an interface with the reconfigurable communication and control fabric. SIMD processing element cells are controlled by the configurable VLIW controller through the reconfigurable communication and control fabric via the interface.

대표청구항 ▼

I claim: 1. A system comprising: a super reconfigurable fabric architecture module, comprising: a configurable very long instruction word controller that receives a control word from a host processor over a standard I/O bus; a reconfigurable communication and control fabric having a very long instr

I claim: 1. A system comprising: a super reconfigurable fabric architecture module, comprising: a configurable very long instruction word controller that receives a control word from a host processor over a standard I/O bus; a reconfigurable communication and control fabric having a very long instruction word interface to said configurable very long instruction word controller; and a single instruction-multiple data processing element cell controlled by said configurable very long instruction word controller through said reconfigurable communication and control fabric via said very long instruction word interface; and a virtual bus interface to the super reconfigurable fabric architecture module, wherein the virtual bus interface comprises: a virtual memory port that maps a standard bus protocol to virtual bus interface signals provided between said virtual bus interface and the super reconfigurable fabric architecture module, wherein said virtual memory port provides a port signal having a type chosen from "data", "control", "fifo", or "bit", wherein each port signal type has a self-processor that performs distinct operations producing processed data, and wherein said processed data is stored in a memory location attached to said virtual memory port. 2. The system of claim 1, wherein said single instruction-multiple data processing element cell further comprises: a coarse grain reconfigurable processing element connected through said very long instruction word interface to said reconfigurable communication and control fabric. 3. The system of claim 1, wherein said single instruction-multiple data processing element cell further comprises: a fine grain reconfigurable cell connected through said very long instruction word interface to said reconfigurable communication and control fabric. 4. The system of claim 1, wherein said single instruction-multiple data processing element cell further comprises: a fine grain reconfigurable cell connected through said very long instruction word interface to said reconfigurable communication and control fabric; and a coarse grain reconfigurable processing element connected through a fine-grain reconfigurable controller interface to said fine grain reconfigurable cell. 5. The system of claim 1, wherein the reconfigurable communication and control fabric further comprises: an interface to a single instruction-multiple data processing element cell; an interface to a floating-point unit; an inter-chip communication module with a "v4" interface to the configurable very long instruction word controller; a data memory controller having a "v6" interface to the configurable very long instruction word controller; and an I/O controller with a "cd" interface to said data memory controller, an "icd" interface to said inter-chip communication module, and a "v5" interface to the configurable very long instruction word controller. 6. The system of claim 5, further comprising: a "pcd" interface between said I/O controller and the single instruction-multiple data processing element cell. 7. The system of claim 5, further comprising: a processing element memory controller with a "pad" interface to the single instruction-multiple data processing element cell and an "mcd" interface to said I/O controller. 8. The system of claim 5, wherein said I/O controller has an "fd" interface to the floating-point unit. 9. The system of claim 1, wherein the single instruction-multiple data processing element cell further comprises: a plurality of processing elements; and a fine grain reconfigurable cell having a fine grain reconfigurable cell controller interface to each of said plurality of processing elements. 10. The system of claim 9, wherein said fine grain reconfigurable cell has a "v2" interface that receives a fine grain reconfigurable cell portion of a very long instruction word. 11. The system of claim 9, wherein said fine grain reconfigurable cell is implemented by a field programmable gate array. 12. The system of claim 9, wherein said plurality of processing elements are configured as a 2횞2 array of n-bit coarse-grain processing elements that communicate through their I/O ports and passing through a reconfigurable control and communication fabric. 13. The system of claim 1, wherein said virtual memory port is glued to an application logic according to the port signal type of said virtual memory port. 14. The system of claim 1, wherein said self-processor includes a look-up table. 15. A field programmable gate array comprising: a virtual bus interface that receives a control word from a host processor over a standard I/O bus; a super reconfigurable fabric architecture module, comprising: a configurable very long instruction word controller that receives said control word via virtual bus interface signals from said virtual bus interface; a reconfigurable communication and control fabric wherein said configurable very long instruction word controller has a very long instruction word interface "v" with said reconfigurable communication and control fabric; and a single instruction-multiple data processing element cell controlled by said configurable very long instruction word controller through said reconfigurable communication and control fabric via said very long instruction word interface "v"; and wherein the virtual bus interface comprises: a virtual memory port that maps a standard bus protocol to virtual bus interface signals provided between said virtual bus interface and the super reconfigurable fabric architecture module, wherein said virtual memory port provides a port signal having one of a plurality of port signal types, wherein each port signal type has a self-processor that performs distinct operations producing processed data, and wherein said processed data is stored in a memory location attached to said virtual memory port. 16. The field programmable gate array of claim 15, wherein said reconfigurable communication and control fabric further comprises an inter-chip communication module wherein said configurable very long instruction word controller has a very long instruction word interface "v4" with said inter-chip communication module. 17. The field programmable gate array of claim 15, wherein said single instruction-multiple data processing element cell further comprises: a fine grain reconfigurable cell wherein said configurable very long instruction word controller has a very long instruction word interface "v2" with said fine grain reconfigurable cell. 18. The field programmable gate array of claim 15, wherein said field programmable gate array is configured in a single instruction-multiple data program mode using said very long instruction word interface "v". 19. The field programmable gate array of claim 15, wherein said field programmable gate array is configured in a multiple single instruction-multiple data program mode using said very long instruction word interface "v". 20. A method for operating a super reconfigurable fabric architecture module to perform parallel processing, the method comprising operations of: interconnecting a single instruction-multiple data processing element cell through a reconfigurable communication and control fabric to a configurable very long instruction word controller; configuring said configurable very long instruction word controller via a control word from a host processor wherein: said configurable very long instruction word controller controls processing in said single instruction-multiple data processing element cell; and said configurable very long instruction word controller controls communication and control in said reconfigurable communication and control fabric; providing a virtual bus interface to the super reconfigurable fabric architecture module, wherein the virtual bus interface comprises: a virtual memory port; mapping, via said virtual memory port, a standard bus protocol to virtual bus interface signals provided between said virtual bus interface and the super reconfigurable fabric architecture module; providing a port signal having one of a plurality of port signal types from said virtual memory port, wherein each port signal type has a self-processor that performs distinct operations producing processed data; and storing said processed data in a memory location attached to said virtual memory port. 21. The method of claim 20, wherein said configuring operation further comprises controlling a plurality of n-bit coarse-grain processing elements in said single instruction-multiple data processing element cell. 22. The method of claim 20, wherein said configuring operation further comprises controlling fine grain reconfigurable cell in said single instruction-multiple data processing element cell. 23. The method of claim 20, further including an operation of providing communication control instructions from said configurable very long instruction word controller for an inter-chip communication module included in said reconfigurable communication and control fabric, wherein said inter-chip communication module controls inter-chip communication between said single instruction-multiple data processing element cell and a second single instruction-multiple data processing element cell.