초록 ▼

The invention concerns a thin layer semi-conductor structure including a semi-conductor surface layer (2) separated from a support substrate (1) by an intermediate zone (3), the intermediate zone (3) being a multi-layer electrically insulating the semi-conductor surface layer from the support substr

The invention concerns a thin layer semi-conductor structure including a semi-conductor surface layer (2) separated from a support substrate (1) by an intermediate zone (3), the intermediate zone (3) being a multi-layer electrically insulating the semi-conductor surface layer from the support substrate. The intermediate zone has a considered sufficiently good electrical quality of interface with the semi-conductor surface layer and includes at least one first layer, of satisfactory thermal conductivity to provide a considered as correct operation of the electronic device or devices which are to be elaborated from the semi-conductor surface layer (2), the intermediate zone including additionally a second insulating layer of low dielectric constant, located between the first layer and the support substrate.

대표청구항 ▼

The invention claimed is: 1. A process for manufacturing a semiconductor structure comprising providing a first substrate and a second substrate, the first substrate comprising a semiconductor surface layer, manufacturing layers comprising the manufacturing of a first layer providing thermal conduc

The invention claimed is: 1. A process for manufacturing a semiconductor structure comprising providing a first substrate and a second substrate, the first substrate comprising a semiconductor surface layer, manufacturing layers comprising the manufacturing of a first layer providing thermal conductivity on the semiconductor surface layer or on the second substrate and the manufacturing of a second layer of an electric insulating material of low dielectric constant on the semiconductor surface layer or on the second substrate such that if the first substrate is bonded to the second substrate, the layers are sandwiched between the semiconductor surface layer and the second substrate with the first layer closer to the first substrate than the second layer, the said layers providing an intermediate zone, bonding the first substrate to the second substrate such that the layers are sandwiched between the semiconductor surface layer and the second substrate with the first layer closer to the first substrate than the second layer, reducing the thickness of the first substrate to provide the semiconductor surface layer of the semiconductor structure, wherein the intermediate zone electrically insulates the semiconductor surface layer from the second substrate and the second layer of the intermediate zone provides bonding by molecular adhesion between the intermediate zone and the second substrate. 2. A process according to claim 1, wherein the second layer is of silicon oxide. 3. A process according to claim 1, wherein the first layer is a layer of a material chosen from among polycrystalline silicon deposited by LPCVD, diamond deposited by PECVD, alumina deposited by reactive cathode sputtering, silicon nitride deposited by CVD, aluminum nitride deposited by CVD, boron nitride deposited by CVD and silicon carbide deposited by CVD. 4. A process according to claim 1, wherein the intermediate zone is manufactured so as to further include a third, electrical insulating, layer between the first layer and the semiconductor surface layer after the bonding step, said third layer providing to the intermediate zone an electrical interface quality. 5. A process according to claim 4, wherein the third layer is a layer of silicon oxide. 6. A process according to claim 4, wherein the third layer is manufactured by thermal oxidation of a silicon surface. 7. A process according to claim 1, wherein bonding the first substrate onto the second substrate is achieved by molecular adhesion. 8. A process according to claim 7, wherein the manufacturing step of the layers of the intermediate zone includes the deposition of at least one bonding layer to allow bonding by molecular adhesion. 9. A process according to claim 8, wherein said bonding layer is a silicon oxide layer. 10. A process according to claim 1, wherein the reduction in the thickness of the first substrate is obtained by using one or more technologies from among rectification, chemical etching, and polishing. 11. A process according to claim 1, wherein the process further comprises a step of ion implantation in the first substrate at a cleavage plane, and wherein the reduction in the thickness of the first substrate is obtained by thermal treatment. 12. A process according to claim 2, wherein bonding the first substrate onto the second substrate is achieved by molecular adhesion. 13. A process according to claim 3, wherein bonding the first substrate onto the second substrate is achieved by molecular adhesion. 14. A process according to claim 4, wherein bonding the first substrate onto the second substrate is achieved by molecular adhesion. 15. A process according to claim 5, wherein bonding the first substrate onto the second substrate is achieved by molecular adhesion. 16. A process according to claim 6, wherein bonding the first substrate onto the second substrate is achieved by molecular adhesion. 17. A process according to claim 2, wherein the reduction in the thickness of the first substrate is obtained by using one or more technologies from among rectification, chemical etching, and polishing. 18. A process according to claim 3, wherein the reduction in the thickness of the first substrate is obtained by using one or more technologies from among rectification, chemical etching, and polishing. 19. A process according to claim 4, wherein the reduction in the thickness of the first substrate is obtained by using one or more technologies from among rectification, chemical etching, and polishing. 20. A process according to claim 5, wherein the reduction in the thickness of the first substrate is obtained by using one or more technologies from among rectification, chemical etching, and polishing. 21. A process according to claim 6, wherein the reduction in the thickness of the first substrate is obtained by using one or more technologies from among rectification, chemical etching, and polishing. 22. A process according to claim 2, wherein the process further comprises a step of ion implantation in the first substrate at a cleavage plane, and wherein the reduction in the thickness of the first substrate is obtained by thermal treatment. 23. A process according to claim 3, wherein the process further comprises a step of ion implantation in the first substrate at a cleavage plane, and wherein the reduction in the thickness of the first substrate is obtained by thermal treatment. 24. A process according to claim 4, wherein the process further comprises a step of ion implantation in the first substrate at a cleavage plane, and wherein the reduction in the thickness of the first substrate is obtained by thermal treatment. 25. A process according to claim 5, wherein the process further comprises a step of ion implantation in the first substrate at a cleavage plane, and wherein the reduction in the thickness of the first substrate is obtained by thermal treatment. 26. A process according to claim 6, wherein the process further comprises a step of ion implantation in the first substrate at a cleavage plane and wherein the reduction in the thickness of the first substrate is obtained by thermal treatment. 27. A process according to claim 1, wherein the thickness of the first layer of the intermediate zone is at least an order of magnitude or greater than a thermal dissipation zone of the semiconductor structure. 28. A process according to claim 1, wherein the first layer is different from the second layer.