Embodiments of the present invention provide a transmitter of a semiconductor device, which can output signals corresponding to input signals having various common mode levels and amplitudes. The transmitter may include a pre-driver unit, main driver unit, and a control circuit. The pre-driver unit
Embodiments of the present invention provide a transmitter of a semiconductor device, which can output signals corresponding to input signals having various common mode levels and amplitudes. The transmitter may include a pre-driver unit, main driver unit, and a control circuit. The pre-driver unit modifies a common mode level and the amplitude of first internal output signals to generate internal output signals in response to driver control signals. The main driver unit modifies the common mode level and the amplitude of the second internal output signals. The control circuit detects the common mode level and the amplitude of a connected circuit. The common mode level and the amplitude of the output signals may then automatically be adjusted to be the same as the common mode level and the amplitude of this connected circuit High speed signal conditioning may be accomplished.
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What is claimed is: 1. A transmitter of a semiconductor device, the transmitter comprising: a pre-driver unit to modify a common mode level and an amplitude of a first internal output signal to generate a second internal output signal in response to a first driver control signal and a first termina
What is claimed is: 1. A transmitter of a semiconductor device, the transmitter comprising: a pre-driver unit to modify a common mode level and an amplitude of a first internal output signal to generate a second internal output signal in response to a first driver control signal and a first termination control signal; a main driver unit to modify a common mode level and an amplitude of the second internal output signal to generate an output signal in response to a second driver control signal and a second termination control signal; and a control circuit to detect a common mode level and an amplitude of an input mode signal corresponding to the output signal to generate the first and second driver control signals and the first and second termination control signals, wherein a common mode level and an amplitude of the output signal are the same as the common mode level and the amplitude of the input mode signal. 2. The transmitter of claim 1, wherein the first internal output signal, the second internal output signal, the output signal, and the input mode signal are differential signals. 3. The transmitter of claim 1, wherein the input mode signal and the output signal are one of transition minimized differential signaling (TMDS), half voltage differential signaling (HVDS), low voltage differential signaling (LVDS), and a rambus signal level (RSL). 4. The transmitter of claim 2, wherein the pre-driver unit comprises: a pre-driver to convert the first internal output signal into the second internal output signal in response to the first driver control signal; and a first termination circuit unit to set a termination voltage supplied to a signal line that transmits one of the second internal output signal in response to the first termination control signal. 5. The transmitter of claim 4, wherein the pre-driver comprises: an output unit to invert the first internal output signal to generate the second internal output signal; a complementary output unit to invert a complementary signal of the first internal output signal to generate a complementary signal of the second internal output signal; a pull-up transistor unit to supply one of a power supply voltage and a first voltage less than the power supply voltage to the output unit and the complementary output unit in response to a pull-up signal included in the first driver control signal; and a pull-down transistor unit to supply one of a ground voltage and a second voltage greater than the ground voltage to the output unit and the complementary output unit in response to a pull-down signal included in the first driver control signal. 6. The transmitter of claim 5, wherein the pull-up transistor unit comprises PMOS transistors, each including a source to which the power supply voltage is applied and a gate to which the pull-up signal is input. 7. The transmitter of claim 5, wherein the pull-down transistor unit comprises NMOS transistors, each including a source to which the ground voltage is applied and a gate to which the pull-down signal is input. 8. The transmitter of claim 4, wherein the termination voltage is one of a power supply voltage, 쩍 of the power supply voltage, and a ground voltage. 9. The transmitter of claim 8, wherein the first termination circuit unit comprises: a first termination circuit to supply the termination voltage to a signal line that transmits the second internal output signal via a termination resistor in response to the first termination control signal; and a first complementary termination circuit to supply the termination voltage to a signal line that transmits a complementary signal of the second internal output signal via the termination resistor in response to the first termination control signal. 10. The transmitter of claim 9, wherein the first termination circuit comprises: an NMOS transistor including a source to which the ground voltage is applied and a gate to which the first termination control signal is input; a first PMOS transistor including a source to which 쩍 of the power supply voltage is applied and a gate to which the first terminal control signal is input; and a second PMOS transistor including a source to which the power supply voltage is applied and a gate to which the first termination control signal is input, wherein the termination resistor is connected between a node connecting drains of the NMOS transistor, the first PMOS transistor, and the second PMOS transistor, and the signal line that transmits the second internal output signal. 11. The transmitter of claim 9, wherein the first complementary termination circuit comprises: an NMOS transistor including a source to which the ground voltage is applied and a gate to which the first termination control signal is input; a first PMOS transistor including a source to which 쩍 of the power supply voltage is applied and a gate to which the first termination control signal is input; and a second PMOS transistor including a source to which the power supply voltage is applied and a gate to which the first termination control signal is input, wherein the termination resistor is connected between a node connecting drains of the NMOS transistor, the first PMOS transistor and the second PMOS transistor, and the signal line that transmits the complementary signal of the second internal output signal. 12. The transmitter of claim 2, wherein the main driver unit comprises: a main driver to convert the second internal output signal into the output signal in response to the second driver control signal; and a second termination circuit unit to set a termination voltage supplied to a signal line that transmits the output signal in response to the second termination control signal. 13. The transmitter of claim 12, wherein the main driver comprises: an output unit to invert the second internal output signal to generate the output signal; a complementary output unit to invert a complementary signal of the second internal output signal to generate a complementary signal of the output signal; a pull-up transistor unit to supply one of a power supply voltage and a first voltage less than the power supply voltage to the output unit and the complementary output unit in response to a pull-up signal included in the second driver control signal; and a pull-down transistor unit to supply one of a ground voltage and a second voltage greater than the ground voltage to the output unit and the complementary output unit in response to a pull-down signal included in the second driver control signal. 14. The transmitter of claim 13, wherein the pull-up transistor unit comprises PMOS transistors, each including a source to which the power supply voltage is applied and a gate to which the pull-up signal is input. 15. The transmitter of claim 13, wherein the pull-down transistor unit comprises NMOS transistors, each including a source to which the ground voltage is applied and a gate to which the pull-down signal is input. 16. The transmitter of claim 12, wherein the termination voltage is one of a power supply voltage, 쩍 of the power supply voltage, and a ground voltage. 17. The transmitter of claim 16, wherein the first termination circuit unit comprises: a first termination circuit to supply the termination voltage to a signal line that transmits the output signal via a termination resistor in response to the second termination control signal; and a complementary termination circuit to supply the termination voltage to a signal line that transmits a complementary signal of the output signal via the termination resistor in response to the second termination control signal. 18. The transmitter of claim 17, wherein the first termination circuit comprises: an NMOS transistor including a source to which the ground voltage is applied and a gate to which the second termination control signal is input; a first PMOS transistor including a source to which 쩍 of the power supply voltage is applied and a gate to which the second termination control signal is input; and a second PMOS transistor including a source to which the power supply voltage is applied and a gate to which the second termination control signal is input, wherein the termination resistor is connected between a node connecting drains of the NMOS transistor, the first PMOS transistor and the second PMOS transistor, and the signal line that transmits the output signal. 19. The transmitter of claim 17, wherein the first complementary termination circuit comprises: an NMOS transistor including a source to which the ground voltage is applied and a gate to which the second termination control signal is input; a first PMOS transistor including a source to which 쩍 of the power supply voltage is applied and a gate to which the second termination control signal is input; and a second PMOS transistor including a source to which the power supply voltage is applied and a gate to which the second termination control signal is input, wherein the termination resistor is connected between a node connecting drains of the NMOS transistor, the first PMOS transistor and the second PMOS transistor, and the signal line that transmits the complementary signal of the output signal. 20. The transmitter of claim 2, wherein the control circuit comprises: a detector to detect the common mode level and the amplitude of the input mode signal to generate a register signal having a first portion of bits and a second portion of bits; a driver register to store the first portion of bits as a first register signal; a mode register to store the second portion of bits as a second register signal; a voltage generator to generate a predetermined bias voltage; a first driver to generate the first and the second driver control signals in response to the first register signal and the bias voltage; and a second driver to generate the first and the second termination control signals in response to the second register signal and the bias voltage. 21. The transmitter of claim 20, wherein the voltage of the first driver control signal, the second driver control signal, the first termination control signal, and the second termination control signal are each adapted to drive a PMOS or an NMOS transistor into saturation. 22. The transmitter of claim 20, wherein the first driver comprises a plurality of inverters. 23. The transmitter of claim 20, wherein the second driver comprises a plurality of inverters. 24. A transmitter of a semiconductor device, the transmitter comprising: a pre-driver to convert first internal output signals into second internal output signals; a main driver unit to modify a common mode level and an amplitude of the second internal output signals to generate output signals in response to driver control signals and termination control signals; and a control circuit to detect a common mode level and an amplitude of input signals corresponding to the output signals to generate the driver control signals and the termination control signals, wherein a common mode level and an amplitude of the output signals are the same as the common mode level and the amplitude of the input signals. 25. The transmitter of claim 24, wherein the first internal output signals, the second internal output signals, the output signals, and the input signals are differential signals. 26. The transmitter of claim 24, wherein the input signals and the output signals are one of transition minimized differential signaling (TMDS), half voltage differential signaling (HVDS), low voltage differential signaling (LVDS), and a rambus signal level (RSL). 27. The transmitter of claim 25, wherein the main driver unit comprises: a main driver to convert the second internal output signals into the output signals in response to the driver control signals; and a termination circuit unit to set a termination voltage supplied to signal lines that transmit the output signals in response to the termination control signals. 28. The transmitter of claim 27, wherein the main driver comprises: an output unit to invert the second internal output signal to generate the output signal; a complementary output unit to invert a complementary signal of the second internal output signal to generate a complementary signal of the output signal; a pull-up transistor unit to supply one of a power supply voltage and a first voltage less than the power supply voltage to the output unit and the complementary output unit in response to pull-up signals included in the driver control signals; and a pull-down transistor unit supplies one of a ground voltage and a second voltage greater than the ground voltage to the output unit and the complementary output unit in response to pull-down signals included in the driver control signals. 29. The transmitter of claim 28, wherein the pull-up transistor unit comprises three PMOS transistors, each including a source to which the power supply voltage is applied and a gate to which one of the pull-up signals is input. 30. The transmitter of claim 28, wherein the pull-down transistor unit comprises three NMOS transistors, each including a source to which the ground voltage is applied and a gate to which one of the pull-down signals is input. 31. The transmitter of claim 27, wherein the termination voltage is one of a power supply voltage, 쩍 of the power supply voltage, and a ground voltage. 32. The transmitter of claim 31, wherein the termination circuit unit comprises: a termination circuit to supply the termination voltage to a signal line that transmits the output signal via a termination resistor in response to the termination control signals; and a complementary termination circuit to supply the termination voltage to a signal line that transmits a complementary signal of the output signal via the termination resistor in response to the termination control signals. 33. The transmitter of claim 32, wherein the first termination circuit comprises: an NMOS transistor including a source to which the ground voltage is applied and a gate to which one of the termination control signals is input; a first PMOS transistor including a source to which 쩍 of the power supply voltage is applied and a gate to which one of the termination control signals is input; and a second PMOS transistor including a source to which the power supply voltage is applied and a gate to which one of the termination control signals is input, wherein the termination resistor is connected between a node connecting drains of the NMOS transistor, the first PMOS transistor, and the second PMOS transistor, and the signal line that transmits the output signal. 34. The transmitter of claim 32, wherein the first complementary termination circuit comprises: an NMOS transistor including a source to which the ground voltage is applied and a gate to which one of the termination control signals is input; a first PMOS transistor including a source to which 쩍 of the power supply voltage is applied and a gate to which one of the termination control signals is input; and a second PMOS transistor including a source to which the power supply voltage is applied and a gate to which one of the termination control signals is input, wherein the termination resistor is connected between a node connecting drains of the NMOS transistor, the first PMOS transistor and the second PMOS transistor, and the signal line that transmit the complementary signal of the output signal. 35. The transmitter of claim 25, wherein the control circuit comprises: a detector to detect the common mode level and the amplitude of the input signals to generate a register signal; a driver register to store some bits of the register signal as a first register signal; a mode register to store the remaining bits of the register signal as a second register signal; a voltage generator to generate a predetermined bias voltage; a first driver to generate the first and the second driver control signals in response to the first register signal and the bias voltage; and a second driver to generate the first and the second termination control signals in response to the second register signal and the bias voltage. 36. The transmitter of claim 35, wherein the voltages of the driver control signals and termination control signals are adapted to drive a PMOS or an NMOS transistor into a saturation mode. 37. The transmitter of claim 35, wherein the first driver comprises a plurality of inverters. 38. The transmitter of claim 35, wherein the second driver comprises a plurality of inverters. 39. A method of transmitting a signal of a semiconductor device: converting a first internal output signal into a second internal output signals; modifying a common mode level and an amplitude of the second internal output signal to generate output signals in response to driver control signals and termination control signals; and detecting a common mode level and an amplitude of input signals corresponding to the output signals to generate the driver control signals and the termination control signals, wherein a common mode level and an amplitude of the output signals are the same as the common mode level and the amplitude of the input signals.
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