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A method of sampling image signals generated by pixel circuits of an active pixel sensor (APS) image sensor. The APS image sensor supports a normal mode of operation and a sub-sampling mode of operation. The method includes providing a plurality of column amplifiers. A row of pixels circuits to sam

A method of sampling image signals generated by pixel circuits of an active pixel sensor (APS) image sensor. The APS image sensor supports a normal mode of operation and a sub-sampling mode of operation. The method includes providing a plurality of column amplifiers. A row of pixels circuits to sample is selected. Image signals from each pixel circuit in the selected row are routed to a different one of the plurality of column amplifiers when the APS image sensor is in the normal mode of operation. Image signals from a plurality of the pixel circuits in the selected row are routed to one of the plurality of column amplifiers when the APS image sensor is in the sub-sampling mode of operation.

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What is claimed is: 1. A method of sampling image signals generated by multi-transistor pixel circuits of an active pixel sensor (APS) image sensor, the APS image sensor supporting a normal mode of operation and a sub-sampling mode of operation, the method comprising: providing a plurality of colum

What is claimed is: 1. A method of sampling image signals generated by multi-transistor pixel circuits of an active pixel sensor (APS) image sensor, the APS image sensor supporting a normal mode of operation and a sub-sampling mode of operation, the method comprising: providing a plurality of column amplifiers separate and distinct from the multi-transistor pixel circuits and coupled to output nodes of the multi-transistor pixel circuits, each column amplifier including an input configured to be coupled to a column of multi-transistor pixel circuits, an input capacitor coupled to the input of the column amplifier, an amplifier circuit, a first switch coupled between the input capacitor and the amplifier circuit, and a first node connected in series with the input capacitor and the first switch and positioned between the input capacitor and the first switch such that the input capacitor is positioned between the input and the first node; providing a plurality of second switches connected to the column amplifiers, each second switch being coupled between the first nodes of two of the column amplifiers; selecting a row of multi-transistor pixels circuits to sample; routing image signals from the output node of each multi-transistor pixel circuit in the selected row to a different one of the plurality of column amplifiers by opening the second switches when the APS image sensor is in the normal mode of operation; and routing image signals from the output nodes of a plurality of the multi-transistor pixel circuits in the selected row to a common one of the plurality of column amplifiers by closing at least some of the second switches when the APS image sensor is in the sub-sampling mode of operation, including exclusively routing multiple image signals from the output nodes of odd column multi-transistor pixel circuits to a common odd column amplifier of the column amplifiers and exclusively routing multiple image signals from the output nodes of even column multi-transistor pixel circuits to a common even column amplifier of the column amplifiers. 2. The method of claim 1, wherein the APS image sensor supports multiple sub-sampling modes of operation, the method further comprising: receiving sub-sample selection information identifying a desired sub-sampling mode of operation, wherein only a subset of the image signals generated by the pixel circuits is sampled in the identified sub-sampling mode. 3. The method of claim 2, wherein the number of pixel circuits in the plurality of pixel circuits in the selected row is determined based on the sub-sample selection information. 4. The method of claim 1, wherein the plurality of pixel circuits in the selected row includes two pixel circuits when the sub-sampling mode of operation is a two-to-one sub-sampling mode. 5. The method of claim 1, wherein the plurality of pixel circuits in the selected row includes four pixel circuits when the sub-sampling mode of operation is a four-to-one sub-sampling mode. 6. The method of claim 1, and further comprising: providing a plurality of switches positioned between the output nodes of the pixel circuits and the plurality of column amplifiers for selectively routing image signals from the output node of each pixel circuit to different ones of the plurality of column amplifiers; and configuring the plurality of switches based on a current mode of operation of the image sensor. 7. An active pixel sensor (APS) image sensor comprising: an array of multi-transistor pixel circuits; a plurality of amplifiers for buffering image signals output by the array of multi-transistor pixel circuits, each amplifier including an input configured to be coupled to a column of multi-transistor pixel circuits, an input capacitor coupled to the input of the amplifier, an amplifier circuit, a first switch coupled between the input capacitor and the amplifier circuit, and a first node connected in series with the input capacitor and the first switch and positioned between the input capacitor and the first switch such that the input capacitor is positioned between the input and the first node; a routing mechanism separate from the array of multi-transistor pixel circuits and positioned between the array of multi-transistor pixel circuits and the plurality of amplifiers, the routing mechanism being connected to the nodes of the amplifiers; and a controller for selecting a subset of the multi-transistor pixel circuits for sampling, the controller configured to control the routing mechanism to connect each multi-transistor pixel circuit in the subset to a different one of the amplifiers during a normal mode of operation, the controller also being configured to exclusively connect multiple odd column multi-transistor pixel circuits in the subset to a common odd column amplifier of the amplifiers and exclusively connected multiple even column multi-transistor pixel circuits in the subset to a common even column amplifier of the amplifiers during a sub-sampling mode of operation. 8. The image sensor of claim 7, wherein the routing mechanism comprises a plurality of switches. 9. The image sensor of claim 8, wherein the plurality of switches are MOSFET transistors. 10. The image sensor of claim 7, wherein the selected subset of pixel circuits is a row of pixel circuits. 11. The image sensor of claim 7, wherein the image sensor supports multiple sub-sampling modes of operation, and wherein the controller is configured to receive sub-sample selection information identifying a desired sub-sampling mode of operation. 12. The image sensor of claim 11, wherein the number of pixel circuits in the multiple pixel circuits in the subset is determined based on the sub-sample selection information. 13. The image sensor of claim 7, wherein the sub-sampling mode of operation is a two-to-one sub-sampling mode, and wherein the multiple pixel circuits in the subset include two pixel circuits. 14. The image sensor of claim 7, wherein the sub-sampling mode of operation is a four-to-one sub-sampling mode, and wherein the multiple pixel circuits in the subset include four pixel circuits. 15. A column amplifier array for a CMOS image sensor, the column amplifier array comprising: a plurality of column amplifiers that are separate and distinct from pixel circuits of the image sensor, each column amplifier including an input configured to be coupled to a column of pixel circuit in the image sensor, an input capacitor coupled to the input of the column amplifier, an amplifier circuit, a first switch coupled between the input capacitor and the amplifier circuit, and a first node connected in series with the input capacitor and the first switch and positioned between the input capacitor and the first switch such that the input capacitor is positioned between the input and the first node; and a second switch coupled between the first nodes of two of the column amplifiers, the second switch configured to be open during a normal mode of operation of the image sensor and configured to be closed during a sub-sample mode of operation of the image sensor. 16. The column amplifier array of claim 15, wherein the column amplifier array includes a plurality of even column amplifiers configured to be coupled to even columns of pixel circuits in the image sensor, and a plurality of odd column amplifiers configured to be coupled to odd columns of pixel circuits in the image sensor. 17. The column amplifier array of claim 16, wherein the second switch is directly connected to the first nodes of two of the even column amplifiers, the column amplifier array further comprising a third switch directly connected to the first nodes of two of the odd column amplifiers. 18. The column amplifier array of claim 16, wherein the first nodes of each of the odd column amplifiers are exclusively connected together with a first plurality of switches, and the first nodes of each of the odd column amplifiers are exclusively connected together with a second plurality of switches. 19. The column amplifier array of claim 18, wherein the first and the second plurality of switches are configured to be opened and closed based on a current mode of operation of the image sensor. 20. The column amplifier array of claim 15, wherein the second switch is a MOSFET transistor.