IPC분류정보
국가/구분 |
United States(US) Patent
등록
|
국제특허분류(IPC7판) |
|
출원번호 |
US-0757964
(2004-01-14)
|
등록번호 |
US-7308056
(2007-12-11)
|
발명자
/ 주소 |
- Pukkila,Markku
- Bysted,Tommy
|
출원인 / 주소 |
|
인용정보 |
피인용 횟수 :
18 인용 특허 :
3 |
초록
▼
This invention discloses improved single antenna interference cancellation (SAIC) receivers utilizing joint channel estimation for suppression of interference of co-channel signals. This invention describes the technique to perform joint channel estimation for either synchronous or asynchronous co-c
This invention discloses improved single antenna interference cancellation (SAIC) receivers utilizing joint channel estimation for suppression of interference of co-channel signals. This invention describes the technique to perform joint channel estimation for either synchronous or asynchronous co-channel signals without a prior knowledge of the interfering training sequence or its timing position. The invented joint channel estimation can require initial detection of the desired signal and can be implemented as a multistage equalization structure.
대표청구항
▼
What is claimed is: 1. A method, comprising: receiving a radio signal by a receiver filter of the single antenna interference cancellation receiver and providing a filtered waveform signal to a joint channel estimator (40) of a joint channel estimator module of the single antenna interference cance
What is claimed is: 1. A method, comprising: receiving a radio signal by a receiver filter of the single antenna interference cancellation receiver and providing a filtered waveform signal to a joint channel estimator (40) of a joint channel estimator module of the single antenna interference cancellation receiver; providing a desired bit decision signal to the joint channel estimator module; and computing a desired impulse response estimate signal by the joint channel estimator using the filtered waveform signal, the desired bit decision signal, and an interfering training sequence signal and an interfering training sequence delay signal generated without prior knowledge of a training sequence of the interfering co-channel signals for suppression of interfering co-channel signals, synchronous and asynchronous, in a single antenna interference cancellation receiver. 2. The method of claim 1, after said providing the desired bit decision signal (창(1)) to the joint channel estimator module, further comprising: computing a replica signal calculated by a replica signal generation means of the joint channel estimator module as a convolution of the desired bit decision signal and a replica impulse response of said replica signal generation means; and generating a residual signal by subtracting the replica signal from the filtered waveform signal using an adder. 3. The method of claim 2, wherein the interfering training sequence and the interfering training sequence delay signal are identified by calculating correlating signals of said residual signal with the candidate training sequences or training sequences convolved by a known transmission pulse shape for all possible bit positions; among said correlating signals, the maximum correlation signal is selected as interfering training sequence and the corresponding timing position as the interfering training sequence delay signal which are provided to the joint channel estimator. 4. The method of claim 1, wherein the interfering signals are asynchronous with a desired signal. 5. The method of claim 1, wherein the interfering signals are synchronous with a desired signal. 6. The method of claim 1, wherein the desired bit decision signal partly comprises a known training bit sequence signal. 7. The method of claim 1, after receiving the radio signal by the receiver filter, further comprises: computing an initial desired impulse response estimate signal using the filtered waveform signal by a channel estimator of a first stage of the single antenna interference cancellation receiver; and computing the desired bit decision signal using the initial desired impulse response estimate signal and the filtered waveform signal by a single antenna interference cancellation detector of the first stage of the single antenna interference cancellation receiver. 8. The method of claim 7, wherein the channel estimator is an iterative constant modulus channel estimator and single antenna interference cancellation detector is a constant modulus single antenna interference cancellation detector. 9. The method of claim 1, after said computing the desired impulse response estimate signal by the joint channel estimator, further comprising: computing a further desired bit decision signal using the desired impulse response estimate signal and the filtered waveform signal by a further single antenna interference cancellation detector of a second stage of the single antenna interference cancellation receiver. 10. The method of claim 9, wherein the further desired bit decision signal is an output signal of the single antenna interference cancellation receiver generated using a predetermined criterion. 11. The method of claim 9, further comprising: providing the further desired bit decision signal to a further joint channel estimator module of a third stage of the single antenna interference cancellation receiver. 12. The method of claim 9, wherein the channel estimator is an iterative constant modulus channel estimator and wherein the single antenna interference cancellation detector and the further single antenna interference cancellation detector are constant modulus single antenna interference cancellation detectors. 13. A single antenna interference cancellation receiver, comprising: a receiver filter of the single antenna interference cancellation receiver, responsive to a radio signal, configured to provide a filtered waveform signal; a means configured to provide a desired bit decision signal; and a joint channel estimator of the single antenna interference cancellation receiver, responsive to the filtered waveform signal, to the desired bit decision signal, and to an interfering training sequence signal and an interfering training sequence delay signal generated without prior knowledge of training sequence of the interfering co-channel signal, configured to provide a desired impulse response estimate signal, wherein said single antenna interference cancellation receiver is for suppression of interfering co-channel signals, both synchronous and asynchronous. 14. The single antenna interference cancellation receiver of claim 13, wherein the means for providing a desired bit decision signal is a first stage of the single antenna interference cancellation receiver, said first stage comprises: a channel estimator, responsive to the filtered waveform signal, for providing configured to provide an initial desired impulse response estimate signal; and a single antenna interference cancellation detector, responsive to the initial desired impulse response estimate signal, configured to provide the desired bit decision signal. 15. The single antenna interference cancellation receiver of claim 13, wherein the channel estimator is an iterative constant modulus channel estimator and single antenna interference cancellation detector is a constant modulus single antenna interference cancellation detector. 16. The single antenna interference cancellation receiver of claim 13, further comprising at least one more stage, responsive to the desired bit decision signal and to the filtered waveform signal, configured to provide further desired bit decision signal. 17. The single antenna interference cancellation receiver of claim 16, wherein the further desired bit decision signal is an output signal of a further single antenna interference cancellation detector generated using a predetermined criterion. 18. The single antenna interference cancellation receiver of claim 16, wherein said at least one more stage that is a second stage comprises: a further single antenna interference cancellation detector, responsive to the desired impulse response estimate signal, configured to provide the further desired bit decision signal; and a joint channel estimator moduler, responsive to the desired bit decision signal and to the filtered waveform signal, configured to provide the desired impulse response estimate signal. 19. The single antenna interference cacellation receiver of claim 18, wherein the channel estimator is an iterative constant modulus channel estimator and wherein the single antenna interference cancellation detector and the further single antenna interference cancellation detector are constant modulus single antenna interference cancellation detectors. 20. The single antenna interference cancellation receiver of claim 18, wherein said joint channel estimator module comprises: a replica signal generation means, responsive to the desired bit decision signal, configured to provide for providing a replica signal calculated as a convolution of the desired bit decision signal and a replica impulse response of said replica signal generation means; an adder, for providing a residual signal by subtracting the replica signal from the filtered waveform signal; a correlation means, responsive to the residual signal, configured to provide the interfering training sequence and its delay signal identified by calculating correlating signals of said residual signal with the candidate training sequences or training sequences convolved by a known transmission pulse shape for all possible bit positions; among said correlating signals, the maximum correlation signal is selected as the interfering training sequence signal and the corresponding timing position as the interfering training sequence delay signal which are provided to the joint channel estimator; and a joint channel estimator, responsive to the filtered waveform signal, to the desired bit decision signal, to the interfering training sequence signal and to the interfering training sequence delay signal, configured to provide the desired impulse response estimate signal. 21. The single antenna interference cancellation receiver of claim 16, further comprising at least one further stage, responsive to the further desired bit decision signal and to the filtered waveform signal, configured to provide at least one further desired bit decision signal.
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