Flexible and scalable architecture for transport processing
원문보기
IPC분류정보
국가/구분
United States(US) Patent
등록
국제특허분류(IPC7판)
H04L-009/00
H04K-001/00
H04J-015/00
G06F-015/16
출원번호
US-0608301
(2003-06-27)
등록번호
US-7334132
(2008-02-19)
발명자
/ 주소
Kumar,Nishit
Vogt,Timothy
출원인 / 주소
Zoran Corporation
대리인 / 주소
Blakely Sokoloff Taylor & Zafman LLP
인용정보
피인용 횟수 :
13인용 특허 :
7
초록▼
A transport processor that can be used in a digital audio-video receiver system comprises a front end and a memory interface. The front end receives concurrently a plurality of transport streams, where two or more of the plurality of transport streams can have different formats, and each transport
A transport processor that can be used in a digital audio-video receiver system comprises a front end and a memory interface. The front end receives concurrently a plurality of transport streams, where two or more of the plurality of transport streams can have different formats, and each transport stream includes a plurality of packets. The front end includes a packet processor to create an aggregate transport stream in a single format from the plurality of transport streams. The memory interface is an interface through which the transport processor can store the aggregate transport stream in a memory for use by subsequent decode and display operations.
대표청구항▼
What is claimed is: 1. A transport processor comprising: a front end to receive concurrently a plurality of transport streams, where two or more of the plurality of transport streams have different formats, each transport stream including a plurality of packets, the front end comprising a packet pr
What is claimed is: 1. A transport processor comprising: a front end to receive concurrently a plurality of transport streams, where two or more of the plurality of transport streams have different formats, each transport stream including a plurality of packets, the front end comprising a packet processor to create an aggregate transport stream in a single format from the plurality of transport streams; and a memory interface through which the transport processor can store the aggregate transport stream in a memory for use by subsequent decode and display operations. 2. The transport processor of claim 1, wherein the number of streams within the aggregate transport stream is scaleable. 3. The transport processor of claim 1, wherein the front end further comprises: a PID filter to discard packets in the aggregate transport stream prior to processing, in order to minimize memory bandwidth and improve descrambling and demultiplexing throughput. 4. The transport processor of claim 1, wherein the aggregation of transport streams permits the use of a single PID filter, a single descrambler, and a single demultiplexer. 5. The transport processor of claim 1, further comprising: a descrambler to descramble the packets in the aggregate transport stream. 6. The transport processor of claim 5, wherein the descrambler comprises: a packet level control and key RAM control logic to select a descrambling standard for a packet within the aggregate transport stream; and a decryption circuit to descramble the packet using the selected descrambling standard. 7. The transport processor of claim 1, wherein: the packet processor further is to format each packet from the plurality of transport streams to said single format prior to storing the aggregate transport stream in the memory. 8. The transport processor of claim 7, wherein the single format is a 208-byte format, and packets with fewer than 208 bytes are padded to comply with the single format. 9. The transport processor of claim 7, wherein the single format includes originating stream information that comprises temporal information. 10. The transport processor of claim 7, wherein the single format includes originating stream information that comprises stream identifier and additional user specified information. 11. The transport processor of claim 7, wherein the single format includes originating stream information. 12. The transport processor of claim 1, wherein the aggregate stream includes transport data obtained from different transport protocol standards. 13. The transport processor of claim 1, further comprising: a plurality of input/output (I/O) ports; an I/O port that is user-selectable to a parallel or serial format. 14. The transport processor of claim 13, wherein the I/O ports comprise: a serial output block to resample parallel data, and to convert the parallel data to serial data with an independently programmable bit clock selection. 15. The transport processor of claim 1, further comprising: a PID filter to discard packets from the aggregate transport stream, retaining only packets of interest; a descrambler to descramble the remaining packets in the aggregate stream; and a demultiplexer to demultiplex the descrambled packets in the aggregate stream; wherein the descrambler and the demultiplexer receive only the packets of interest. 16. The transport processor of claim 1, further comprising: a switching matrix to select a subset of the streams out of a plurality of streams for storage and subsequent descrambling and demultiplexing. 17. The transport processor of claim 16, wherein the switching matrix comprises: a delay circuit to switch to a new stream after receiving an end of packet signal from an original stream, such that only complete packets from the original stream are propagated. 18. The transport processor of claim 17, wherein the switching matrix further comprises: a data valid signal to indicate that the output of the switching matrix is valid only after an end of packet signal is received from the new stream, such that only complete packets from the new stream are propagated. 19. The transport processor of claim 1, further comprising: a demultiplixer to demultiplex an aggregate transport stream retrieved from the memory, into a plurality of different streams, for use by said decode and display operations. 20. The transport processor of claim 19, further comprising a descrambler to receive the aggregate transport stream from the memory via the memory interface and to provide a descrambled version of the aggregate transport stream to the demultiplexer. 21. A system on a chip (SOC) comprising: a transport processor to PID filter, descramble, and demultiplex a plurality of transport streams, the transport processor including: a front end to concurrently receive a plurality of transport streams, where two or more of the transport streams have different formats, and a packet processor to create an aggregate transport stream having a single format from the plurality of transport streams; a memory to store demultiplexed outputs of the plurality of transport streams; and an output processor to retrieve one or more demultiplexed outputs from the memory and perform audio/video decode and display functions simultaneously. 22. The SOC of claim 21, wherein the output processor is a combination of digital audio decoder, digital video decoder, audio processor, and display processor. 23. The SOC of claim 22, wherein the audio and video frames for two independent transport streams are rendered without repeated or skipped frames. 24. The SOC of claim 21, wherein the transport processor further comprises: a readback logic to read packets from the memory, for descrambling and demultiplexing functions. 25. The SOC of claim 21, further comprising a memory interface for use by the transport processor and the output processor to access contents of the memory. 26. A front end in a transport processor to receive a plurality of transport streams from digital receivers, comprising: a switching matrix to receive concurrently the plurality of transport streams, where two or more of the plurality of transport streams have different formats, and to output a programmable subset of the plurality of transport streams; a packet processor to receive the subset of the plurality of transport streams and to aggregate the subset of the plurality of streams into a single aggregate transport stream in a single format. 27. The front end of claim 26, further comprising: a memory to store the aggregate transport stream. 28. The front end of claim 27, further comprising: a PID filter to discard packets, retaining only packets of interest. 29. The front end of claim 27, further comprising: an external input/output (I/O) to receive the plurality of transport streams, the external I/O having a plurality of bi-directional ports. 30. The front end of claim 29, wherein each of the bi-directional ports can be configured as either a single parallel or a pair of serial ports. 31. The front end of claim 30, wherein a bi-directional port includes a serial input block to receive serial input and generate a synchronized parallel output. 32. The front end of claim 30, wherein a bi-directional port includes a serial output block to generate a serial transport stream with an independent bit clock for output. 33. The front end of claim 26, wherein the switching matrix comprises: a stream select delay unit to ensure that only compete packets are propagated. 34. The front end of claim 26, wherein the packet processor is further to attach appropriate header and footer information to transport packets in the subset of the plurality of transport streams. 35. The packet processor in the front end of claim 34, wherein the packet processor generates packets of a uniform size, regardless of originating protocol. 36. A digital audio/video receiver system comprising, on a single chip: a transport processor including: a front end, the front end including: a switching matrix to receive concurrently a plurality of transport streams, including video and audio, each including a plurality of packets, where two or more of the plurality of transport streams have different media formats, each transport stream including a plurality of packets, a PID filter to filter out packets that do not meet specified criteria, and a packet processor to create an aggregate transport stream in a single format from the plurality of transport streams; a memory interface through which the transport processor can store the aggregate transport stream in a memory for subsequent processing; a descrambler to descramble packets read from the memory, and a demultiplixer to demultiplex packets read from the memory, for use by subsequent decode and display operations; a digital decoder to perform video processing functions including decompression of video received from the memory and to store processed video in the memory; an audio processor to perform audio processing functions including audio decompression on audio received from the memory and to generate an audio output of said digital audio/video receiver system; a graphics processor to process graphics; and a display processor to produce a display output of said digital audio/video receiver system by combining processed graphics and video from a plurality of sources to generate a display in any of a plurality of different display formats. 37. A method comprising: receiving concurrently, in a digital audio/video receiver system, a plurality of transport streams which have a plurality of different formats, each transport stream including a plurality of packets; creating an aggregate transport stream in a single format from the plurality of transport streams in said digital audio/video receiver system; and storing the aggregate transport stream in a memory for use by subsequent decode and display operations. 38. The method of claim 37, further comprising: demultiplexing an aggregate transport stream retrieved from the memory into a plurality of different streams, for use by said decode and display operations. 39. The method of claim 38, further comprising: descrambling the aggregate transport stream retrieved from the memory.
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이 특허에 인용된 특허 (7)
James Shirley J. (Southampton GB2), Data decoder adapted to decode data of different rates and/or encoded formats.
Civanlar Mehmet R. (Middletown NJ) Gaglianello Robert D. (Little Silver NJ), Multiple resolution, multi-stream video system using a single standard coder.
Hoffert, Bradley W.; Hoffert, Susanna E.; Kelsey, Steven L.; McPeak, James L.; Medina, Oscar I.; Fitzpatrick, Christopher E.; Wilcox, Paul A., Inline audio/visual conversion.
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