초록 ▼

Stacked inverter delay chains. In accordance with a first embodiment of the present invention, a series stack of two p-type devices is coupled to a series stack of three n-type devices, forming a stacked inverter comprising desirable delay, die area and power characteristics. Two stacked inverters

Stacked inverter delay chains. In accordance with a first embodiment of the present invention, a series stack of two p-type devices is coupled to a series stack of three n-type devices, forming a stacked inverter comprising desirable delay, die area and power characteristics. Two stacked inverters are coupled together to form a stacked inverter delay chain that is more efficient in terms of die area, active and passive power consumption than conventional delay chains comprising conventional inverters.

대표청구항 ▼

What is claimed is: 1. A method of delaying a signal comprising: inverting said signal using a first stacked inverter circuit to produce an inverted signal at an output of said first stacked inverter circuit; propagating said inverted signal to an input of a second stacked inverter circuit; and pro

What is claimed is: 1. A method of delaying a signal comprising: inverting said signal using a first stacked inverter circuit to produce an inverted signal at an output of said first stacked inverter circuit; propagating said inverted signal to an input of a second stacked inverter circuit; and producing a delayed version of said signal at an output of said second stacked inverter circuit, wherein said second stacked inverter circuit includes a total number of transistors of a first type that is different than a total number of a second type. 2. A method according to claim 1 wherein said second stacked inverter circuit comprises two p-type devices and three n-type devices. 3. A method according to claim 1 wherein said inverting is performed over a greater time duration compared to an inverting performed by an inverter comprising only two active devices. 4. A method according to claim 1 wherein said propagating said inverted signal is performed using a substantially direct connection to said output of said first stacked inverter circuit. 5. A method according to claim 1 wherein said producing is performed over a greater time duration compared to an inverting performed by an inverter comprising only two active devices. 6. A method according to claim 1 embodied in an integrated circuit. 7. A method according to claim 6 wherein said integrated circuit comprises a microprocessor. 8. A stacked inverter circuit comprising: a first number of devices of a first type coupled in series; a second number of devices of an opposite type coupled in series; and wherein said first number of devices and said second number of devices are coupled in series and a total of said first number of devices is not equal to a total of said second number of devices. 9. A stacked inverter circuit of claim 8 characterized in having a greater switching time duration than an inversion performed by an inverter comprising only two active devices. 10. A stacked inverter circuit of claim 8 characterized in having less leakage current than an inverter comprising only two active devices. 11. A stacked inverter circuit of claim 8 wherein a gate of each device is coupled to receive an input signal. 12. A stacked inverter circuit of claim 8 wherein: said first type is a p-type; and said opposite type is an n-type. 13. A stacked inverter delay circuit comprising: two stacked inverter circuits coupled in series, each of said stacked inverter circuits comprising: at least two devices of a first type coupled in series; at least three devices of an opposite type coupled in series; and wherein a total number of said devices of said first type is different from a total number of said devices of said opposite type. 14. A stacked inverter delay circuit of claim 13 wherein said two stacked inverter circuits are substantially identical. 15. A stacked inverter delay circuit of claim 14 wherein each of said stacked inverter circuits comprises two p-type devices. 16. A stacked inverter delay circuit of claim 15 wherein each of said stacked inverter circuits comprises three n-type devices. 17. A stacked inverter delay circuit of claim 13 characterized in having a greater delay time duration than a delay created by two stages of inverters, each of said stages comprising only two devices. 18. A stacked inverter delay circuit of claim 13 characterized in having less leakage current than a delay circuit comprising two stages of inverters, each of said stages comprising only two devices. 19. A stacked inverter delay circuit of claim 13 wherein a gate of all devices of each stacked inverter is coupled to the input signal. 20. A stacked inverter delay circuit of claim 13 wherein said first type is p-type. 21. A stacked inverter delay circuit of claim 13 wherein said first type is n-type. 22. An integrated circuit comprising: a first device of a first type comprising a first terminal coupled to an operating voltage; a second device of said first type comprising a first terminal coupled to a second terminal of said first device; a third device of an opposite type comprising a first terminal coupled to a second terminal of said second device; a fourth device of said opposite type comprising a first terminal coupled to a second terminal of said third device; a fifth device of said opposite type comprising a first terminal coupled to a second terminal of said fourth device; said fifth device further comprising a second terminal coupled to a ground reference of said integrated circuit, wherein third terminals of said first, second, third, fourth and fifth devices are coupled together forming an input to said integrated circuit; an output of said integrated circuit coupled to said second terminal of said second device; and wherein a total number of said devices of said first type is different from a total number of said devices of said opposite type. 23. The integrated circuit of claim 22 wherein said first type is p-type. 24. The integrated circuit of claim 23 wherein said opposite type is n-type.