초록 ▼

A programmable logic integrated circuit has an embedded processor with a watchdog timer circuit. The watchdog timer circuit is used to detect software or hardware failures. In one implementation, the watchdog timer circuit includes a counter register that advances (e.g., incremented or decremented)

A programmable logic integrated circuit has an embedded processor with a watchdog timer circuit. The watchdog timer circuit is used to detect software or hardware failures. In one implementation, the watchdog timer circuit includes a counter register that advances (e.g., incremented or decremented) with each clock. To prevent the watchdog timer circuit from becoming triggered, the watchdog timer circuit should be reset or reloaded by software. For example, the count register may be reset to a value to start the count over. If the count register is allowed to count to a final or maximum value, the watchdog timer circuit will become triggered, generating a triggered signal that causes the programmable logic integrated circuit to be reset. A reset causes a reloading of the configuration data used to program the programmable logic and embedded processor portions of the integrated data. The configuration data may be stored in an external nonvolatile storage memory.

대표청구항 ▼

What is claimed is: 1. A method of operating a programmable logic integrated circuit comprising: loading an initial value in a count register that is a part of a watchdog timer circuit integrated as part of a programmable logic integrated circuit disposed on a single die; clocking the count registe

What is claimed is: 1. A method of operating a programmable logic integrated circuit comprising: loading an initial value in a count register that is a part of a watchdog timer circuit integrated as part of a programmable logic integrated circuit disposed on a single die; clocking the count register to advance the count register to a next value with each clock; periodically reloading the count register with the initial value, wherein the reloading is caused by receiving a first magic value, wherein the first magic value when received configures the watchdog timer circuit to respond to a second magic value that is different from the first magic value, wherein the second magic value when received configures the watchdog timer circuit to respond to a third magic value that is different from the second magic value, wherein after receiving the first magic value, upon receiving the second magic value, resetting the watchdog timer circuit to the initial value, wherein after receiving the second magic value, upon receiving the third magic value, resetting the watchdog timer circuit to the initial value; when the stored count value held in the count register that is a part of the watchdog timer circuit reaches a final value, asserting a triggered signal output; and upon receiving the triggered signal output in a reset logic block on the programmable logic integrated circuit, causing reloading of configuration data from an external source into the programmable logic integrated circuit. 2. The method of claim 1 wherein the external source is a nonvolatile memory. 3. The method of claim 1 wherein the external source is a serial EPROM. 4. The method of claim 1 wherein the final value causes an overflow condition for the count register that is a part of the watchdog timer circuit. 5. The method of claim 1 wherein the watchdog timer circuit increments the stored count value at each clock pulse. 6. The method of claim 1 wherein the watchdog timer circuit decrements the stored count value at each clock pulse. 7. The method of claim 1 wherein periodically reloading the count register comprises: writing the first magic value into a reload register that is a part of the watchdog timer circuit; and when the first magic value is received in the reload register, resetting the count register that is a part of the watchdog timer circuit to the initial value. 8. The method of claim 1 further comprising: using the configuration data to configure an embedded processor portion and a programmable logic portion on the programmable logic integrated circuit. 9. The method of claim 1 wherein to avoid asserting the triggered signal output, a periodic reload of the watchdog timer circuit should be performed during a time period it takes the watchdog timer circuit to count from the initial value to the final value. 10. The method of claim 9 wherein the period is less than about two minutes. 11. The method of claim 9 wherein the time period depends on clock frequency used to clock the watchdog timer circuit. 12. The method of claim 1 wherein the initial value is 0 and the final value is a maximum count value permitted by the count register. 13. The method of claim 1 wherein the count register comprises 32 bits. 14. A method of operating a programmable logic integrated circuit comprising: clocking a watchdog timer circuit on the programmable logic integrated circuit to advance a count register that is a part of the watchdog timer circuit wherein the programmable logic integrated circuit and the watchdog timer circuit are disposed on the same die; loading a first magic value into a reload register that is a part of the watchdog timer circuit, which resets the count register to an initial value wherein the first magic value when loaded configures the watchdog timer circuit to respond to a second magic value that is different from the first magic value, wherein the second magic value when loaded into the reload register configures the watchdog timer circuit to respond to a third magic value that is different from the second magic value; after loading the first magic value, loading the second magic value into the reload register, which causes the count register to reset the initial value; after loading the first magic value into the reload register, loading a value other than the second magic value or the third magic value into the reload register, which causes the watchdog timer circuit to generate a triggered signal; and receiving the triggered signal in a reset logic block on the programmable logic integrated circuit, which causes a reloading of configuration data from an external source into the programmable logic integrated circuit, wherein the watchdog timer circuit is configured in response to the second magic value to respond to a the third magic value that is different from the first and second magic values. 15. The method of claim 14 wherein the configuration data is used to configure an embedded processor portion and a programmable logic portion on the programmable logic integrated circuit. 16. The method of claim 14 wherein the watchdog timer circuit is located in an embedded processor portion and the reset logic block is located in a programmable logic portion on the programmable logic integrated circuit. 17. The method of claim 14 further comprising: allowing the count register that is a part of the watchdog timer circuit to advance to a final value before the first or second magic values are loaded, which causes the watchdog timer circuit to generate the triggered signal. 18. The method of claim 14 wherein the initial value is 0. 19. The method of claim 14 wherein the initial value is a value other than 0. 20. The method of claim 17 wherein the final value is user-selectable. 21. The method of claim 17 wherein the final value is the maximum count permitted by the count register. 22. The method of claim 14 wherein in a debug mode, the count register does not advance.