Configurable IC with interconnect circuits that also perform storage operations
원문보기
IPC분류정보
국가/구분
United States(US) Patent
등록
국제특허분류(IPC7판)
H01L-025/00
H03K-019/177
출원번호
US-0081859
(2005-03-15)
등록번호
US-7342415
(2008-03-11)
발명자
/ 주소
Teig,Steven
Schmit,Herman
Redgrave,Jason
Chandra,Vikas
출원인 / 주소
Tabula, Inc.
대리인 / 주소
Adeli & Tollen LLP
인용정보
피인용 횟수 :
65인용 특허 :
114
초록▼
Some embodiments provide a configurable IC that includes several configurable logic circuits for configurably performing computations. The configurable IC also includes several configurable routing circuits for configurable routing signals to and from the logic circuits. In some embodiments, at leas
Some embodiments provide a configurable IC that includes several configurable logic circuits for configurably performing computations. The configurable IC also includes several configurable routing circuits for configurable routing signals to and from the logic circuits. In some embodiments, at least a set of the routing circuits are routing/storage circuits. Each routing/storage circuit has an output and a storage section at the output for controllably storing a signal that the routing/storage circuit produces at the output.
대표청구항▼
We claim: 1. An integrated circuit (IC) comprising: a) a plurality of configurable logic circuits for configurably performing computations; and b) a plurality of configurable interconnect circuits for configurably passing signals to and from said logic circuits; c) wherein at least a set of the int
We claim: 1. An integrated circuit (IC) comprising: a) a plurality of configurable logic circuits for configurably performing computations; and b) a plurality of configurable interconnect circuits for configurably passing signals to and from said logic circuits; c) wherein at least a set of the interconnect circuits are interconnect/storage circuits, wherein each interconnect/storage circuit comprises (i) a multi-stage multiplexer that has an output stage, and (ii) a storage section at the output stage for controllably storing a signal that the interconnect/storage circuit produces at the output stage. 2. The IC of claim 1, wherein the storage section of each interconnect/storage circuit is established in the multi-stage multiplexer of the interconnect/storage. 3. The IC of claim 2, wherein the storage section of the interconnect/storage circuit is not in front of the multi-stage multiplexer. 4. The IC of claim 1, wherein the multi-stage multiplexer uses the output stage even when the interconnect/storage circuit does not store a signal. 5. The IC of claim 4, wherein the storage section of an interconnect/storage circuit is built in the output stage of the multi-stage multiplexer. 6. The IC of claim 4, wherein the storage section of an interconnect/storage circuit is cross-coupled to the output stage of the multi-stage multiplexer. 7. The IC of claim 1, wherein the storage section is established by selectively establishing a feedback path in the output stage. 8. The IC of claim 7, wherein the feedback path is established by cross coupling two signals in the output stage. 9. The IC of claim 8, wherein the two signals are a complementary pair of signals. 10. An electronic device comprising: an integrated circuit (IC) comprising: a plurality of configurable logic circuits for configurably performing computations; and a plurality of configurable interconnect circuits for configurably passing signals to and from said logic circuits; wherein at least a set of the interconnect circuits are interconnect/storage circuits, wherein each interconnect/storage circuit comprises (i) a multi-stage multiplexer that has an output stage, and (ii) a storage section at the output stage for controllably storing a signal that the interconnect/storage circuit produces at the output stage. 11. The electronic device of claim 10, wherein the storage section of each interconnect/storage circuit is established in the multi-stage multiplexer of the interconnect/storage. 12. The electronic device of claim 11, wherein the storage section of the interconnect/storage circuit is not in front of the multi-stage multiplexer. 13. The electronic device of claim 10, wherein the multi-stage multiplexer uses the output stage even when the interconnect/storage circuit does not store a signal. 14. The electronic device of claim 13, wherein the storage section of an interconnect/storage circuit is built in the output stage of the multi-stage multiplexer. 15. The electronic device of claim 13, wherein the storage section of an interconnect/storage circuit is cross-coupled to the output stage of the multi-stage multiplexer. 16. The electronic device of claim 10, wherein the storage section is established by selectively establishing a feedback path in the output stage. 17. The electronic device of claim 16, wherein the feedback path is established by cross coupling two signals in the output stage. 18. The electronic device of claim 17, wherein the two signals are a complementary pair of signals. 19. The electronic device of claim 10, wherein the output of the interconnect/storage circuit is fed back to a particular input of the interconnect/storage circuit. 20. The electronic device of claim 19, wherein the interconnect/storage circuit comprises a set of inputs and a set of select lines to select one of its inputs for output, wherein the interconnect/storage circuit acts as storage when the select lines select the particular input that receives the fed back output, wherein the interconnect/storage circuit does not act as storage when the select lines do not select the particular input that receives the fed back output. 21. The IC of claim 1, wherein at least one interconnect/storage circuit reconfigures at run time to act either as a storage circuit or as an interconnect circuit. 22. The IC of claim 1, wherein the storage section of an interconnect/storage circuit is not in signal path flow and does not cause signal path delays when the interconnect/storage circuit is not storing a signal in the storage section. 23. The IC of claim 1, wherein the output of the interconnect/storage circuit is fed back to a particular input of the interconnect/storage circuit. 24. The IC of claim 23, wherein the interconnect/storage circuit comprises a set of inputs and a set of select lines to select one of its inputs for output, wherein the interconnect/storage circuit acts as storage when the select lines select the particular input that receives the fed back output, wherein the interconnect/storage circuit does not act as storage when the select lines do not select the particular input that receives the fed back output. 25. The IC of claim 1, wherein the interconnect circuits are routing circuits. 26. An integrated circuit (IC) comprising: a) a plurality of configurable logic circuits for configurably performing computations; and b) a plurality of configurable interconnect circuits for configurably passing signals to and from said logic circuits; c) wherein at least a set of the interconnect circuits are interconnect/storage circuits comprising (i) an interconnect section that includes an output stage and (ii) a storage section for controllably storing a signal that the interconnect/storage circuit produces, wherein the storage section is cross coupled to the output stage of the interconnect section. 27. The IC of claim 26, wherein the storage section stores the signal by passing a complimentary pair of the signal through the cross coupled wires to the output stage of the interconnect/storage circuit. 28. The IC of claim 26 further comprising configuration data storage for supplying configuration data sets to the storage section, wherein the configuration data sets control whether the storage section stores the signal. 29. An integrated circuit (IC) comprising: a) a plurality of configurable logic circuits for configurably performing computations; and b) a plurality of configurable interconnect circuits for configurably passing signals to and from said logic circuits; c) wherein at least a set of the interconnect circuits are interconnect/storage circuits, wherein each interconnect/storage circuit has an output stage and a storage section at the output stage for controllably storing a signal that the interconnect/storage circuit produces at the output stage, wherein the storage section is established by selectively establishing a feedback path in the output stage, wherein the feedback path is established by cross coupling two signals in the output stage. 30. The IC of claim 29, wherein the two signals are a complimentary pair of signals. 31. An integrated circuit (IC) comprising: a) a plurality of configurable logic circuits for configurably performing computations; and b) a plurality of configurable interconnect circuits for configurably passing signals to and from said logic circuits; c) wherein at least a set of the interconnect circuits are interconnect/storage circuits, wherein each interconnect/storage circuit has an output and a storage section for controllably storing a signal that the interconnect/storage circuit produces at the output, wherein the output of the interconnect/storage circuit is fed back to a particular input of the interconnect/storage circuit. 32. The IC of claim 31, wherein the interconnect/storage circuit comprises a set of inputs and a set of select lines to select one of its inputs for output, wherein the interconnect/storage circuit acts as storage when the select lines select the particular input that receives the fed back output. 33. The IC of claim 31, wherein the interconnect/storage circuit comprises a set of inputs and a set of select lines to select one of its inputs for output, wherein the interconnect/storage circuit does not act as storage when the select lines do not select the particular input that receives the fed back output. 34. An electronic device comprising: an integrated circuit (IC) comprising: a) a plurality of configurable logic circuits for configurably performing computations; and b) a plurality of configurable interconnect circuits for configurably passing signals to and from said logic circuits; c) wherein at least a set of the interconnect circuits are interconnect/storage circuits comprising (i) an interconnect section that includes an output stage and (ii) a storage section for controllably storing a signal that the interconnect/storage circuit produces, wherein the storage section is cross coupled to the output stage of the interconnect section. 35. An electronic device comprising: an integrated circuit (IC) comprising: a) a plurality of configurable logic circuits for configurably performing computations; and b) a plurality of configurable interconnect circuits for configurably passing signals to and from said logic circuits; c) wherein at least a set of the interconnect circuits are interconnect/storage circuits, wherein each interconnect/storage circuit has an output stage and a storage section at the output stage for controllably storing a signal that the interconnect/storage circuit produces at the output stage by selectively establishing a feedback path in the output stage, wherein the feedback path is established by cross coupling two signals in the output stage. 36. An electronic device comprising: an integrated circuit (IC) comprising: a) a plurality of configurable logic circuits for configurably performing computations; and b) a plurality of configurable interconnect circuits for configurably passing signals to and from said logic circuits; c) wherein at least a set of the interconnect circuits are interconnect/storage circuits, wherein each interconnect/storage circuit has an output and a storage section for controllably storing a signal that the interconnect/storage circuit produces at the output, wherein the output of the interconnect/storage circuit is fed back to a particular input of the interconnect/storage circuit.
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Swami,Parvesh; Khanna,Namerita; Agarwal,Deepak, Architecture for programmable logic device.
Trimberger Stephen M. (San Jose CA) Carberry Richard A. (Los Gatos CA) Johnson Robert A. (San Jose CA) Wong Jennifer (Fremont CA), Configuration modes for a time multiplexed programmable logic device.
Wakayama Shigetoshi,JPX ; Gotoh Kohtaroh,JPX ; Saito Miyoshi,JPX ; Ogawa Junji,JPX, Destructive read type memory circuit, restoring circuit for the same and sense amplifier.
Nguyen Bai ; Agrawal Om P. ; Sharpe-Geisler Bradley A. ; Wong Jack T. ; Chang Herman M., Efficient interconnect network for use in FPGA device having variable grain architecture.
Agrawal, Om P.; Fontana, Fabiano; Bosco, Gilles M., Enhanced CPLD macrocell module having selectable bypass of steering-based resource allocation and methods of use.
Tavana Danesh (Mountain View CA) Yee Wilson K. (Tracy CA) Holen Victor A. (Saratoga CA), FPGA architecture with repeatable tiles including routing matrices and logic matrices.
Iadanza Joseph Andrew ; Kilmoyer Ralph David ; Laramie Michael Joseph ; Seidel Victor Paul ; Zittritsch Terrance John, Field programmable memory array.
Bennett David Wayne (Louisville CO) Dellinger Eric Ford (Boulder CO) Manaker ; Jr. Walter A. (Boulder CO) Stern Carl M. (Boulder CO) Troxel William R. (Longmont CO) Young Jay Thomas (Louisville CO), Frequency driven layout and method for field programmable gate arrays.
Rostoker Michael D. ; Koford James S. ; Scepanovic Ranko ; Jones Edwin R. ; Padmanahben Gobi R. ; Kapoor Ashok K. ; Kudryavtsev Valeriy B.,RUX ; Andreev Alexander E.,RUX ; Aleshin Stanislav V.,RUX ; , Hexagonal field programmable gate array architecture.
Vorbach,Martin; M체nch,Robert, Internal bus system for DFPS and units with two-or multi-dimensional programmable cell architectures, for managing large volumes of data with a high interconnection complexity.
Goetting F. Erich (Cupertino CA) Trimberger Stephen M. (San Jose CA), Logic cell for field programmable gate array having optional internal feedback and optional cascade.
Norman Kevin A. ; Patel Rakesh H. ; Sample Stephen P. ; Butts Michael R., Look-up table based logic element with complete permutability of the inputs to the secondary signals.
Chiang David (Saratoga CA) Lee Napoleon W. (Fremont CA) Ho Thomas Y. (Milpitas CA) Harrison David A. (Cupertino CA) Kucharewski ; Jr. Nicholas (Pleasanton CA) Seltzer Jeffrey H. (San Jose CA), Macrocell with product-term cascade and improved flip flop utilization.
Clinton Kim P. N. ; Iadanza Joseph Andrew ; Keyser ; III Frank Ray ; Seidel Victor Paul ; Zittritsch Terrance John, Memory cells for field programmable memory array.
Poplingher Mircea ; Chen Wenliang ; Suryanarayanan Ganesh ; Chen Wayne W. ; Lo Roger Y., Memory device for a microprocessor register file having a power management scheme and method for copying information between memory sub-cells in a single clock cycle.
Larsen Wendell Ray (Essex Junction VT) Keyser Frank Ray (Colchester VT) Worth Brian A. (Milton VT), Memory mapping method and apparatus to fold sparsely populated structures into densely populated memory columns or rows.
Fuller Christine Marie ; Hartman Steven Paul ; Millham Eric Ernest, Method and system for optimizing a critical path in a field programmable gate array configuration.
Craft David John ; Gould Scott Whitney ; Keyser ; III Frank Ray ; Worth Brian, Method and system for programming a gate array using a compressed configuration bit stream.
Bailis, Robert Thomas; Kuhlmann, Charles Edward; Lingafelt, Charles Steven; Rincon, Ann Marie, Method and system for use of a field programmable function within a chip to enable configurable I/O signal timing characteristics.
Bailis, Robert Thomas; Kuhlmann, Charles Edward; Lingafelt, Charles Steven; Rincon, Ann Marie, Method and system for use of a field programmable function within a standard cell chip for repair of logic circuits.
Bailis, Robert Thomas; Kuhlmann, Charles Edward; Lingafelt, Charles Steven; Rincon, Ann Marie, Method and system for use of a field programmable interconnect within an ASIC for configuring the ASIC.
Bailis, Robert Thomas; Kuhlmann, Charles Edward; Lingafelt, Charles Steven; Rincon, Ann Marie, Method and system for use of an embedded field programmable gate array interconnect for flexible I/O connectivity.
Gould Scott Whitney ; Iadanza Joseph Andrew ; Keyser ; III Frank Ray ; Zittritsch Terrance John, Method of operating a field programmable memory array with a field programmable gate array.
Trimberger Stephen M. (San Jose CA) Carberry Richard A. (Los Gatos CA) Johnson Robert A. (San Jose CA) Wong Jennifer (Fremont CA), Method of time multiplexing a programmable logic device.
Gould Scott Whitney ; Iadanza Joseph Andrew ; Keyser ; III Frank Ray ; Zittritsch Terrance John, Programmable address decoder for field programmable memory array.
Clinton Kim P. N. (Essex Junction VT) Gould Scott W. (South Burlington VT) Hartman Steven P. (Jericho VT) Iadanza Joseph A. (Hinesburg VT) Keyser ; III Frank R. (Colchester VT) Millham Eric E. (St. G, Programmable array interconnect network.
El Gamal Abbas A. (Palo Alto CA) El-Ayat Khaled A. (Cupertino CA) Greene Jonathan W. (Palo Alto CA) Guo Ta-Pen R. (Cupertino CA) Reyneri Justin M. (Los Altos CA), Programmable interconnect architecture.
Motomura Masato,JPX, Programmable logic IC having memories for previously storing a plurality of configuration data and a method of reconfigurating same.
New Bernard J. ; Johnson Robert Anders ; Wittig Ralph ; Mohan Sundararajarao, Rapidly reconfigurable FPGA having a multiple region architecture with reconfiguration caches useable as data RAM.
Blodget, Brandon J.; McMillan, Scott P.; James-Roxby, Philip B.; Sundararajan, Prasanna; Keller, Eric R.; Curd, Derek R.; Kalra, Punit S.; LeBlanc, Richard J.; Eck, Vincent P., Reconfiguration of a programmable logic device using internal control.
Om P. Agrawal ; Claudia A. Stanley ; Xiaojie (Warren) He ; Larry R. Metzger ; Robert A. Simon ; Kerry A. Ilgenstein, Scalable architecture for high density CPLD's having two-level hierarchy of routing resources.
Clinton Kim P. N. ; Gould Scott Whitney ; Iadanza Joseph Andrew ; Keyser ; III Frank Ray ; Kilmoyer Ralph David ; Laramie Michael Joseph ; Seidel Victor Paul ; Zittritsch Terrance John, Selective connectivity between memory sub-arrays and a hierarchical bit line structure in a memory array.
Agrawal Om P. ; Chang Herman M. ; Sharpe-Geisler Bradley A. ; Tran Giap H., Symmetrical, extended and fast direct connections between variable grain blocks in FPGA integrated circuits.
Iadanza Joseph Andrew ; Keyser ; III Frank Ray ; Kilmoyer Ralph David ; Laramie Michael Joseph, System for implementing write, initialization, and reset in a memory array using a single cell write port.
Balasubramanian,Rabindranath; Zhu,Limin; Speers,Theodore; Bakker,Gregory, System-on-a-chip integrated circuit including dual-function analog and digital inputs.
Trimberger Stephen M. (San Jose CA) Carberry Richard A. (Los Gatos CA) Johnson Robert Anders (San Jose CA) Wong Jennifer (Fremont CA), Time multiplexed programmable logic device.
Sale, Darian Robert Peter; Deol, Mandeep Singh; Marshall, Paul Ian Strathdee; Gingrich, Paul Arthur; Pang, Shing Fu; Yang, Victor Xi; Waterson, Andrew Edward; Clynes, Steven Derrick, Device pin mux configuration solving and code generation via Boolean satisfiability.
Redgrave, Jason; Caldwell, Andrew; Teig, Steven, Method and apparatus for performing an operation with a plurality of sub-operations in a configurable IC.
Schmit, Herman; Butts, Michael; Hutchings, Brad L.; Teig, Steven, Method of mapping a user design defined for a user design cycle to an IC with multiple sub-cycle reconfigurable circuits.
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