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[미국특허] Wafer-level burn-in and test 원문보기

IPC분류정보
국가/구분 United States(US) Patent 등록
국제특허분류(IPC7판)
  • G01R-031/02
출원번호 US-0458375 (2006-07-18)
등록번호 US-7345493 (2008-03-18)
발명자 / 주소
  • Khandros,Igor Y.
  • Pedersen,David V.
출원인 / 주소
  • FormFactor, Inc.
대리인 / 주소
    Burraston,N. Kenneth
인용정보 피인용 횟수 : 10  인용 특허 : 81

초록 ▼

Techniques for performing wafer-level burn-in and test of semiconductor devices include a test substrate having active electronic components such as ASICs mounted to an interconnection substrate or incorporated therein, metallic spring contact elements effecting interconnections between the ASICs an

대표청구항 ▼

What is claimed is: 1. Method of performing burn-in on semiconductor devices, comprising: electrically connecting first terminals of a test substrate to second terminals of at least one semiconductor device (DUT) by compressing a plurality of electrically conductive spring contact elements between

이 특허에 인용된 특허 (81) 인용/피인용 타임라인 분석

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  8. Tsujide Tohru (Tokyo JPX) Hishii Toshiyasu (Tokyo JPX) Nakaizumi Kazuo (Tokyo JPX), Apparatus for testing semicondctor wafer.
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  12. Okubo Masao (Tokyo JPX) Yoshimitsu Yasuro (Tokyo JPX), Complex probe card for testing a semiconductor wafer.
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  13. Kwon Oh-Kyong (Richardson TX) Malhi Satwinder (Garland TX) Hashimoto Masahi (Garland TX), Compliant contact pad.
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  24. Bove Ronald (Wappingers Falls NY) Hubacher Eric M. (Wappingers Falls NY), High density wafer contacting and test system.
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  31. Kister January (Palo Alto CA), Large scale protrusion membrane for semiconductor devices under test with very high pin counts.
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  32. Leedy Glenn J. (1061 E. Mountain Dr. Santa Barbara CA 93108), Making and testing an integrated circuit using high density probe points.
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  33. Kasukabe Susumu (Yokohama JPX) Takagi Ryuichi (Tokyo JPX), Manufacturing method of a probe head for semiconductor LSI inspection apparatus.
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  34. Chong,Fu Chiung; Mok,Sammy, Massively parallel interface for electronic circuit.
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  42. Farnworth Warren M. (Nampa ID) Akram Salman (Boise ID) Wood Alan G. (Boise ID), Method for forming contact pins for semiconductor dice and interconnects.
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  43. DeHaven Robert Keith (Austin TX) Wenzel James F. (Austin TX), Method for manufacturing a stimulus wafer for use in a wafer-to-wafer testing system to test integrated circuits located.
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  44. Lum Thomas F. (Austin TX) Wenzel James F. (Austin TX), Method for probing a semiconductor wafer.
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  45. Eldridge Benjamin N. ; Grube Gary W. ; Khandros Igor Y. ; Mathieu Gaetan L., Method of burning-in semiconductor devices.
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  46. Eldridge Benjamin N. ; Grube Gary W. ; Khandros Igor Y. ; Mathieu Gaetan L., Method of exercising semiconductor devices.
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  49. Khandros Igor Y. (Peekskil NY), Method of manufacturing electrical contacts, using a sacrificial member.
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  51. Eldridge Benjamin N. ; Grube Gary W. ; Khandros Igor Y. ; Mathieu Gaetan L., Method of mounting resilient contact structures to semiconductor devices.
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  52. Eldridge Benjamin N. ; Grube Gary W. ; Khandros Igor Y. ; Mathieu Gaetan L., Method of planarizing tips of probe elements of a probe card assembly.
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  53. Watanabe Takashi,JPX ; Yoshida Minako,JPX, Method of producing micro contact structure and contact probe using same.
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  54. Eldridge Benjamin N. ; Grube Gary W. ; Khandros Igor Y. ; Mathieu Gaetan L., Method of temporarily, then permanently, connecting to a semiconductor device.
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  55. Eldridge Benjamin N. ; Grube Gary W. ; Khandros Igor Y. ; Mathieu Gaetan L., Method of testing semiconductor.
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  56. Palagonia Anthony Michael ; Pikna Paul Joseph ; Maddix John Thomas, Micro probe assembly and method of fabrication.
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  57. Swapp Mavin (Mesa AZ), Micromachined semiconductor probe card.
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  58. Eldridge Benjamin N. ; Grube Gary W. ; Khandros Igor Y. ; Mathieu Gaetan L., Mounting spring elements on semiconductor devices.
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  59. Beha Johannes G. (Wdenswil NY CHX) Dreyfus Russell W. (Mt. Kisco NY) Rubloff Gary W. (Katonah NY), Noncontact dynamic tester for integrated circuits.
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  60. Iino Shinji (Yamanashi-ken JPX) Iida Itaru (Yamanashi-ken JPX), Probe apparatus having burn-in test function.
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  61. Okubo Masao (Nishinomiya JPX) Murakami Nobuyuki (Amagasaki JPX) Katahira Kouji (Kikuchi-gun JPX) Iwata Hiroshi (Otokuni-gun JPX) Okubo Kazumasa (Naka-gun JPX), Probe card for maintaining the position of a probe in high temperature application.
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  62. Bordes, Philippe; Ruellou, Pierre, Quantizing method and device for video compression.
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  63. Yamada Toshio (Osaka JPX) Fujiwara Atsushi (Kyoto JPX) Inoue Michihiro (Nara JPX) Matsuyama Kazuhiro (Osaka JPX), Semiconductor testing apparatus, semiconductor testing circuit chip, and probe card.
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  66. Dozier ; II Thomas H. ; Eldridge Benjamin N. ; Grube Gary W. ; Khandros Igor Y. ; Mathieu Gaetan L., Sockets for electronic components and methods of connecting to electronic components.
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  71. Rostoker Michael D. (San Jose CA) Dangelo Carlos (San Jose CA) Koford James (San Jose CA), Testing and exercising individual, unsingulated dies on a wafer.
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  72. Rostoker Michael D. ; Dangelo Carlos ; Koford James, Testing and exercising individual, unsingulated dies on a wafer.
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  73. Arnaudov Konstantin (Wertheim-Bettingen DEX) Prokopp Manfred (Wertheim DEX), Testing device for testing electrical or electronic test specimens.
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  74. Yoshizaki Tsutomu (Yokosuka JPX), Testing equipment for electric components.
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  75. Forehand Monty A. ; Street David R., Voltage margin testing using an embedded programmable voltage source.
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  76. Atkins Glen G. (Boise ID) Cohen Michael S. (Boise ID) Mauritz Karl H. (Eagle ID) Shaffer James M. (Boise ID 4), Wafer scale burn-in apparatus and process.
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  77. Khandros Igor Y. ; Pedersen David V., Wafer-level burn-in and test.
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  78. Khandros, Igor Y.; Pedersen, David V., Wafer-level burn-in and test.
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  79. Khandros, Igor Y.; Pedersen, David V., Wafer-level burn-in and test.
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  80. Khandros,Igor Y.; Pedersen,David V., Wafer-level burn-in and test.
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  81. Eldridge Benjamin N. ; Grube Gary W. ; Khandros Igor Y. ; Mathieu Gaetan L., Wafer-level test and burn-in, and semiconductor process.
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이 특허를 인용한 특허 (10) 인용/피인용 타임라인 분석

  1. Hung, Tsung-Yang, Apparatus for mass die testing.
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  2. Park, Chan, Flip-chip packages allowing reduced size without electrical shorts and methods of manufacturing the same.
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  3. Kemmerling, Todd Ryland, Method and apparatus for processing failures during semiconductor device testing.
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  4. Berry, Tommie Edward; Sporck, Alistair Nicholas, Method and apparatus for testing devices using serially controlled intelligent switches.
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  5. Berry, Tommie Edward; Sporck, Alistair Nicholas, Method and apparatus for testing devices using serially controlled intelligent switches.
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  6. Berry, Tommie Edward, Method and apparatus for testing devices using serially controlled resources.
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  7. Kemmerling, Todd Ryland, Method and apparatus for testing semiconductor devices with autonomous expected value generation.
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  8. Miller, Charles A; Chraft, Matthew E; Henson, Roy J, Method of designing an application specific probe card test system.
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  9. Eldridge, Benjamin N.; Khandros, Igor Y.; Mathieu, Gaetan L.; Pedersen, David V., Microelectronic spring contact elements.
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  10. Khandros, Igor Y.; Pedersen, David V., Wafer-level burn-in and test.
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