초록 ▼

Embodiments of methods in accordance with the present invention provide three-dimensional carbon nanotube (CNT) integrated circuits comprising layers of arrays of CNT's separated by dielectric layers with conductive traces formed within the dielectric layers to electrically interconnect individual C

Embodiments of methods in accordance with the present invention provide three-dimensional carbon nanotube (CNT) integrated circuits comprising layers of arrays of CNT's separated by dielectric layers with conductive traces formed within the dielectric layers to electrically interconnect individual CNT's. The methods to fabricate three-dimensional carbon nanotube FET integrated circuits include the selective deposition of carbon nanotubes onto catalysts selectively formed on a conductive layer at the bottom of openings in a dielectric layer. The openings in the dielectric layer are formed using suitable techniques, such as, but not limited to, dielectric etching, and the formation of ring gate electrodes, including spacers, that provide openings for depositing self-aligned carbon nanotube semiconductor channels.

대표청구항 ▼

What is claimed is: 1. An integrated circuit comprising: a first dielectric layer; a first via of the first dielectric layer; a first conductive pad disposed on the first dielectric layer or in the first via of the first dielectric layer; a second dielectric layer having a thickness and defining a

What is claimed is: 1. An integrated circuit comprising: a first dielectric layer; a first via of the first dielectric layer; a first conductive pad disposed on the first dielectric layer or in the first via of the first dielectric layer; a second dielectric layer having a thickness and defining a second via and a third via, the second and third vias extending through the thickness of the second dielectric layer, the second via in communication with the first conductive pad, and the third via disposed coaxially to the first via and electrically insulated from the first conductive pad; a carbon nanotube semiconductor material disposed in the second via and through the thickness of the second dielectric layer, and correspondingly in communication with the first conductive pad; a conductive material disposed in the third via and through the thickness of the second dielectric layer, the conductive material electrically insulated from the carbon nanotube semiconductor material to form a ring gate electrode; and a third dielectric layer disposed over the second dielectric layer and including a second conductive pad in communication with a selected one of the carbon nanotube semiconductor material in the second via and the conductive material. 2. The integrated circuit of claim 1, further comprising: a first substrate upon which the first dielectric layer is disposed. 3. The integrated circuit of claim 1, further comprising: a passivation layer disposed on the third dielectric layer and second conductive pads. 4. The integrated circuit of claim 1, wherein the first, the second, and the third dielectric layers define one integrated circuit transistor substrate, the integrated circuit further comprising: one or more additional integrated circuit transistor substrates disposed thereon, wherein the second conductive pad of the one integrated circuit transistor substrate are in electrical communication with a first conductive pad of an adjacent series-connected integrated circuit transistor substrate of the one or more additional integrated circuit transistor substrates, providing that the carbon nanotube semiconductor material of one integrated circuit transistor substrate is in series connection with only a carbon nanotube semiconductor material of an adjacent integrated circuit transistor substrate. 5. The integrated circuit of claim 1, wherein the carbon nanotube semiconductor material comprises a selected one of a p-type material converted from an n-type material and an n-type material converted from a p-type material, and wherein the integrated circuit further comprises another carbon nanotube semiconductor material disposed in another via in the second dielectric material and comprising the non-selected one of the p-type material converted from the n-type material and the n-type material converted from the p-type material. 6. The integrated circuit of claim 1, wherein the first, the second, and the third dielectric layers define one integrated circuit transistor substrate, the integrated circuit further comprising: one or more additional integrated circuit transistor substrates disposed thereon, wherein the second conductive pad of the one integrated circuit transistor substrate are in electrical communication with the first conductive pad of an adjacent series-connected integrated circuit transistor substrate of the one or more additional integrated circuit transistor substrates. 7. The integrated circuit of claim 6, wherein the first conductive pad forms a selected one of a source and a drain, and the second conductive pad forms the non-selected one of the source and the drain.