초록 ▼

A remote access device is disclosed for capturing, digitizing and communicating video signals from a host computer to a remote computer. The remote computer returns keyboard and mouse signals through the remote access device to the host computer to control the host computer as though the remote keyb

A remote access device is disclosed for capturing, digitizing and communicating video signals from a host computer to a remote computer. The remote computer returns keyboard and mouse signals through the remote access device to the host computer to control the host computer as though the remote keyboard and mouse were directly connected to the host computer. The remote access device includes a circuit module interface for the host computer that allows the remote access device to operate independently of any operating system characteristics associated with the host computer.

대표청구항 ▼

What is claimed is: 1. A computer circuit coupled to a data bus and communicating with a Host PC, comprising: a video input buffering circuit receiving RGB video signals from the Host PC; an analog to digital converter circuit coupled to the video input buffering circuit to receive and digitize the

What is claimed is: 1. A computer circuit coupled to a data bus and communicating with a Host PC, comprising: a video input buffering circuit receiving RGB video signals from the Host PC; an analog to digital converter circuit coupled to the video input buffering circuit to receive and digitize the RGB video signals; a main gate array circuit to receive the digitized RGB video signals from the analog to digital converter circuit; a video memory circuit to store the digitized RGB video signals; a second gate array circuit coupled to the main gate array circuit, the second gate array circuit bridging data between the main gate array circuit and the data bus; a system clock circuit providing clock signals to the main and second gate array circuits; a main cpu, communicating with the main and second gate array circuits to direct data between the video memory circuit and the second gate array circuit, the main gate array also controlling data traffic between the analog to digital converter circuit, the video memory circuit, and the main cpu; a keyboard cpu in communication with the main cpu and at least one of an external keyboard and an external mouse; and a pixel clock generator to provide a pixel clock signal to the analog to digital converter circuit, the pixel clock generator reproducing in frequency and phase a host pixel clock signal used by the Host PC to produce the RGB video signals received by the video input buffering circuit. 2. A computer circuit according to claim 1, wherein the video memory is a combination of interleaved video RAMs. 3. A computer circuit according to claim 1, wherein the video input buffering circuit includes operational amplifiers, one for each R, G, and B component of the RGB video signal. 4. A computer circuit according to claim 1, wherein the main gate array circuit includes a checksum section to determine a checksum difference between two video frames of the RGB video signal. 5. A computer circuit according to claim 1, wherein the main gate array circuit includes a checksum section to determine a checksum difference between two video frames of the RGB video signal and delivers the checksum difference to the second gate array circuit. 6. A computer circuit according to claim 1, wherein the video memory circuit includes a video RAM and a palette RAM, the main gate array circuit including a checksum section to derive a checksum difference between video frame information in the video RAM versus the palette RAM. 7. A computer circuit according to claim 1, wherein the second gate array circuit includes a timing and control section. 8. A computer circuit according to claim 1, wherein the second gate array circuit includes a video format decoding section. 9. A computer circuit according to claim 1, wherein the second gate array circuit including a video latch area. 10. A computer circuit according to claim 1, wherein the pixel clock generator includes a phase locked loop. 11. A computer circuit according to claim 1, wherein the second gate array circuit includes a video format decoding section generating a vertical blanking period signal and the pixel clock generator includes a sample and hold circuit receiving the vertical blanking period signal at a hold input of said sample and hold circuit said sample and hold circuit having a hold period greater than a maximum vertical flanking period. 12. A computer circuit according to claim 1, further including: an ID switch to uniquely identify the circuit conununicating with the Host PC in comparison to other circuits communicating with other Host PCs via the data bus. 13. A computer circuit according to claim 1, wherein the main gate array circuit and the second gate array circuit are comprised in a single gate array.