[특허]Method of fabricating a semiconductor multi-package module having inverted land grid array (LGA) package stacked over ball grid array (BGA) package

[미국특허] Method of fabricating a semiconductor multi-package module having inverted land grid array (LGA) package stacked over ball grid array (BGA) package 원문보기

IPC분류정보
국가/구분	United States(US) Patent 등록
국제특허분류(IPC7판)	H01L-021/00 H01L-021/02
출원번호	US-0626272 (2007-01-23)
등록번호	US-7364946 (2008-04-29)
발명자 / 주소	Karnezos,Marcos
출원인 / 주소	Chippac, Inc.
인용정보	피인용 횟수 : 10 인용 특허 : 113

초록 ▼

A method is provided for making a semiconductor multi-package module, by providing a lower molded ball grid array package including a lower substrate and a die, affixing an upper molded package including an upper substrate in inverted orientation onto the upper surface of the lower package, and form

대표청구항 ▼

What is claimed is: 1. A method for making a multipackage module, comprising: providing a BGA first package comprising a first package substrate, said BGA first package being a molded package, the molding having a generally planar upper surface; providing a second package comprising a second package substrate; inverting the second package and stacking the inverted second package over the first package, wherein stacking the inverted second package over the first package comprises applying an adhesive onto the molding upper surface and placing the inverted second package onto the adhesive; and electrically interconnecting the first and second package by wire bonds connecting the first and second substrates. 2. The method of claim 1 wherein the adhesive is a curable adhesive, and further comprising curing the adhesive. 3. The method of claim 1 wherein providing the BGA first package comprises providing an unsingulated strip of BGA packages. 4. The method of claim 1 where providing the BGA first package comprises testing BGA packages for a performance and reliability requirement and identifying the said first package as meeting the requirement. 5. The method of claim 1 where providing the second package comprises testing packages for a performance and reliability requirement and identifying the said second package as meeting the requirement. 6. The method of claim 1, further comprising attaching second-level interconnect balls onto the BGA first package substrate. 7. The method of claim 1, further comprising encapsulating the stacked packages in a multipackage module molding. 8. The method of claim 1, further comprising singulating the modules. 9. The method of claim 1 wherein providing the second package comprises providing a land grid array package. 10. The method of claim 1 wherein providing the second package comprises providing a land grid array package, the land grid array package being at least partially molded. 11. The method of claim 10, the land grid array package being fully molded. 12. The method of claim 10, the wire bonds of the land grid array package being molded, and at least a portion of an upward facing surface of an upper die being exposed. 13. The method of claim 1 wherein the BGA first package is provided with an electromagnetic shield affixed over the die. 14. The method of claim 13, the shield having a generally planar upper surface, wherein stacking the inverted second package over the first package comprises applying an adhesive onto the shield upper surface and placing the inverted second package onto the adhesive. 15. The method of claim 14 wherein the adhesive is a curable adhesive, and further comprising curing the adhesive. 16. The method of claim 1, further comprising providing a heat spreader. 17. The method of claim 16, wherein providing a heat spreader comprises carrying out a drop-in mold operation, the heat spreader being placed into a mold prior to forming a module molding. 18. The method of claim 16, wherein providing a heat spreader comprises affixing a generally planar portion of a heat spreader onto a generally planar upward facing surface of the inverted second package.

이 특허에 인용된 특허 (113) 인용/피인용 타임라인 분석

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Jeansonne Jeff K., Opposed ball grid array mounting.
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Terui, Makoto, Semiconductor device.
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Tamaki Kazuo,JPX ; Saza Yasuyuki,JPX ; Dotta Yoshihisa,JPX, Semiconductor device using a chip scale package.
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Mori Ryuichiro,JPX, Semiconductor module comprising semiconductor packages.
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Karnezos,Marcos; Carson,Flynn, Semiconductor multi-package module having inverted bump chip carrier second package.
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Liao, Chih-Chin; Pu, Han-PIng; Huang, Chien-Ping, Semiconductor package.
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Tzu Chung-Hsing,TWX, Semiconductor package having multi-dies.
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Huang, Chien-Ping, Semiconductor package with flash-proof device.
상세보기
Akram, Salman; Brooks, Jerry M., Semiconductor package with stacked substrates and multiple semiconductor dice.
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De Givry Jacques (Les Loges En Josas FRX), Solid state memory modules and memory devices including such modules.
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Yang,Chaur Chin; Wang,Hsueh Te, Stack type flip-chip package.
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Warren M. Farnworth ; Alan G. Wood ; Mike Brooks, Stackable semiconductor package having conductive layer and insulating layers and method of fabrication.
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상세보기
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Degani, Yinon; Dudderar, Thomas Dixon; Sun, Liguo; Zhao, Meng, Stacked module package.
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Kikuma, Katsuhito; Ikeda, Mitsutaka; Tsukidate, Yoshihiro; Akashi, Yuji; Ozawa, Kaname; Takashima, Akira; Nishimura, Takao, Stacked semiconductor device and method of producing the same.
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Baek, Joong-hyun; Lee, Jin-yang; Im, Yun-hyeok; Lee, Tae-koo, Stacked semiconductor module and method of manufacturing the same.
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Pedron, Jr., Serafin P., Stacked semiconductor package and method of manufacturing the same.
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Rostoker Michael D. (Boulder Creek CA), Techniques for providing high I/O count connections to semiconductor dies.
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Distefano Thomas H., Thermally enhanced packaged semiconductor assemblies.
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Hawke Robert E.,CAX ; Patel Atin J.,CAX ; Binapal Sukhminder S.,CAX ; Divita Charles,CAX ; McNeil Lynn,CAX ; Fletcher Thomas G.,CAX, Three dimensional packaging configuration for multi-chip module assembly.
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Lin Paul T. (Austin TX), Three-dimensional multi-chip pad array carrier.
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Massit Claude (Ismier FRX) Nicolas Grard (Voreppe FRX), Three-dimensional multichip module.
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Burns Carmen D. (Austin TX) Roane Jerry (Austin TX) Cady James W. (Austin TX), Ultra high density integrated circuit packages.
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[미국특허] Method of fabricating a semiconductor multi-package module having inverted land grid array (LGA) package stacked over ball grid array (BGA) package 원문보기

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[미국특허] Method of fabricating a semiconductor multi-package module having inverted land grid array (LGA) package stacked over ball grid array (BGA) package 원문보기

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이 특허에 인용된 특허 (113) 인용/피인용 타임라인 분석

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