Catalytic nucleation monolayer for metal seed layers
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IPC분류정보
국가/구분
United States(US) Patent
등록
국제특허분류(IPC7판)
H01L-021/44
H01L-021/02
출원번호
US-0269402
(2005-11-07)
등록번호
US-7365011
(2008-04-29)
발명자
/ 주소
Lavoie,Adrien R.
Fajardo,Arnel
Dubin,Valery M.
출원인 / 주소
Intel Corporation
대리인 / 주소
Engineer,Rahul D.
인용정보
피인용 횟수 :
5인용 특허 :
1
초록▼
A method of forming a copper interconnect on a substrate comprises providing a substrate that includes a dielectric layer and a trench etched into the dielectric layer, depositing a barrier layer within the trench, using a palladium immobilization process to form a metal catalyst layer on the barrie
A method of forming a copper interconnect on a substrate comprises providing a substrate that includes a dielectric layer and a trench etched into the dielectric layer, depositing a barrier layer within the trench, using a palladium immobilization process to form a metal catalyst layer on the barrier layer, activating the metal catalyst layer, and using a vapor deposition process to deposit a copper seed layer onto the metal catalyst layer. The vapor deposition process may include PVD, CVD, or ALD. An electroplating process or an electroless plating process may then be used to deposit a bulk copper layer onto the copper seed layer to fill the trench. A planarization process may follow to form the final interconnect structure.
대표청구항▼
The invention claimed is: 1. A method comprising: providing a substrate that includes a dielectric layer and a trench etched into the dielectric layer; depositing a barrier layer onto the dielectric layer and within the trench; applying a azo-silyl moiety and a metal catalyst to the substrate, wher
The invention claimed is: 1. A method comprising: providing a substrate that includes a dielectric layer and a trench etched into the dielectric layer; depositing a barrier layer onto the dielectric layer and within the trench; applying a azo-silyl moiety and a metal catalyst to the substrate, wherein the metal catalyst couples to the barrier layer by means of the azo-silyl moiety; activating the metal catalyst; using a vapor deposition process to deposit a metal seed layer onto the metal catalyst; and using an electroplating process to deposit a bulk metal layer onto the metal seed layer. 2. The method of claim 1, wherein the substrate is a semiconductor wafer. 3. The method of claim 1, wherein the barrier layer comprises at least one of tantalum, tantalum nitride, tantalum carbide, or tantalum carbonitride. 4. The method of claim 1, wherein the depositing of the barrier layer comprises using a vapor deposition process to deposit the barrier layer onto the dielectric layer and within the trench. 5. The method of claim 1, wherein the metal catalyst comprises at least one of palladium, platinum, ruthenium, iridium, rhenium, rhodium, or osmium. 6. The method of claim 1, wherein the applying of the azo-silyl moiety and the metal catalyst to the substrate comprises applying a first solution to the substrate that includes the azo-silyl moiety and applying a second solution to the substrate that includes the metal catalyst. 7. The method of claim 1, wherein the applying of the azo-silyl moiety and the metal catalyst to the substrate comprises applying a solution to the substrate that includes both the azo-silyl moiety and the metal catalyst. 8. The method of claim 1, wherein the activating of the metal catalyst comprises applying a reducing agent to the metal catalyst. 9. The method of claim 8, wherein the applying of the reducing agent comprises applying at least one solution to the metal catalyst that includes the reducing agent. 10. The method of claim 1, wherein the vapor deposition process comprises physical vapor deposition, chemical vapor deposition, or atomic layer deposition. 11. The method of claim 1, wherein the metal seed layer comprises a copper seed layer. 12. The method of claim 1, wherein the bulk metal layer comprises a bulk copper layer. 13. The method of claim 1, wherein using the electroplating process to deposit the bulk metal layer comprises filling the trench with a metal layer. 14. The method of claim 11, wherein the vapor deposition process uses an organometallic precursor containing copper to form the copper seed layer. 15. The method of claim 14, wherein the organometallic precursor comprises at least one of bis(N,N'-di-sec-butylacetamidinato)copper, bis(N,N'-di-isopropylacetamidinato)copper, bis(N,N'-di-isopropyldimethylaminoacetamidinato)copper, (VTMS)Cu(I)β-diketiminate (where VTMS=vinyltrimetylsilyl), (VTMS)Cu(I)amidinates, copper methoxypropylamidinates, Cu(II) dimethylaminoethoxide, Cu(II) bis(2,2,6,6-tetramethyl-3,5-heptanedionate), Cu(II) bis(2,2-dimethyl-3,5-heptanedionate), Cu(II) bis(2,2-dimethylhexanedionate), Cu(II) bis(acetylacetonate), Cu(II) bis(hexafluoroacetylacetate), Cu methyl(trimethyl)acetyl-thioacetate, Cu methylthiocarboxylate triphenylphosphine, Cu(I) hexamethyldisilazane, CuI, CuBr2, CuBr, CuCl, CuI2, cyclopentadienyl-Cu(I)-triethylphosphine, cyclopentadienyl-Cu(I)-trimethylphosphine, cyclopentadienyl copper (I) triphenylphosphine, Cu(I) tert-butoxide tetramer, Cu(II)methoxide, Cu(II) bis(dimethyldithiocarbamate), Cu(II) bis(diethyldithiocarbamate), Cu(II) bis(diisobutyldithiocarbamate), Cu(II) bis(methyl-butyl-dithiocarbamate), Cu(II) bis(methylhexyldithiocarbamate), Cu (II)(ethoxide), Cu(II)dimethylaminoethoxide, Cu(I)hfac-VTMS, Cu(II)(1-phenyl-1,3-butanedione)2, Cu(II)(1-(2-thienyl)-1,3-butanedione)2, Cu(II)(1,3-(2-thienyl)-1,3-propanedione)2, Cu(acac)2, and Cu(thd)2. 16. The method of claim 4, wherein the vapor deposition process to deposit the barrier layer comprises physical vapor deposition, chemical vapor deposition, or atomic layer deposition. 17. The method of claim 1, further comprising cleaning the substrate after depositing the barrier layer and before applying the azo-silyl moiety and the metal catalyst to the substrate. 18. The method of claim 1, further comprising performing a chemical mechanical polishing process on the substrate after the deposition of the bulk metal layer. 19. A method comprising: providing a substrate including a dielectric layer and a trench etched into the dielectric layer; depositing a barrier layer within the trench; using a wet chemical metal-immobilization-process surface treatment to form a metal catalyst layer on the barrier layer; activating the metal catalyst layer; using a vapor deposition process to fill the trench with a metal layer, wherein the vapor deposition process uses at least one organometallic precursor selected from the group consisting of bis(N,N'-di-sec-butylacetamidinato)copper, bis(N,N'-di-isopropylacetamidinato)copper, bis(N,N'-di-isopropyldimethylaminoacetamidinato)copper, (VTMS)Cu(I)β-diketiminate (where VTMS=vinyltrimetylsilyl), (VTMS)Cu(I)amidinates, copper methoxypropylamidinates, Cu(II) dimethylaminoethoxide, Cu(II) bis(2,2,6,6-tetramethyl-3,5-heptanedionate), Cu(II) bis(2,2-dimethyl-3,5-heptanedionate), Cu(II) bis(2,2-dimethylhexanedionate), Cu(II) bis(acetylacetonate), Cu(II) bis(hexafluoroacetylacetate), Cu methyl(trimethyl)acetyl-thioacetate, Cu methylthiocarboxylate triphenylphosphine, Cu(I) hexamethyldisilazane, CuI, CuBr2, CuBr, CuCl, CuI2, cyclopentadienyl-Cu(I)-triethylphosphine, cyclopentadienyl-Cu(I)-trimethylphosphine, cyclopentadienyl copper (I) triphenylphosphine, Cu(I) tert-butoxide tetramer, Cu(II)methoxide, Cu(II) bis(dimethyldithiocarbamate), Cu(II) bis(diethyldithiocarbamate), Cu(II) bis(diisobutyldithiocarbamate), Cu(II) bis(methyl-butyl-dithiocarbamate), Cu(II) bis(methylhexyldithiocarbamate), Cu(II)(ethoxide), Cu(II)dimethylaminoethoxide, Cu(I)hfac-VTMS, Cu(II)(1-phenyl-1,3-butanedione)2, Cu(II)(1-(2-thienyl)-1,3-butanedione)2, Cu(II) (1,3-(2-thienyl)-1,3-propanedione)2, Cu(acac)2, and Cu(thd)2; and planarizing the substrate to form an interconnect. 20. The method of claim 19, wherein the barrier layer comprises at least one of tantalum, tantalum nitride, tantalum carbide, or tantalum carbonitride. 21. The method of claim 19, wherein the metal catalyst layer comprises a palladium layer. 22. The method of claim 21, wherein the activating of the palladium layer comprises reducing the palladium metal from an oxidized state to a Pd0 state. 23. The method of claim 19, wherein the vapor deposition process comprises PVD, CVD, or ALD. 24. A method comprising: providing a substrate including a dielectric layer and a trench etched into the dielectric layer; depositing a barrier layer within the trench; using a palladium immobilization process to form a palladium layer on the barrier layer and to activate the palladium layer; using a vapor deposition process to deposit a copper seed layer onto the activated palladium layer; using an electroless plating process to deposit a bulk copper layer onto the copper seed layer; and planarizing the substrate to form a copper interconnect. 25. The method of claim 24, wherein the vapor deposition process comprises PVD, CVD, or ALD.
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이 특허에 인용된 특허 (1)
Imori,Toru; Kumagai,Masashi; Sekiguchi,Junnosuke, Metal plating method, pretreatment agent, and semiconductor wafer and semiconductor device obtained using these.
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