초록 ▼

A non-volatile ferroelectric memory device senses a cell data at high speed. Preferably, the non-volatile ferroelectric memory device includes a plurality of cell array blocks, a plurality of sense amplifier units, a plurality of sense amplifier units, a plurality of local data buses, a global data

A non-volatile ferroelectric memory device senses a cell data at high speed. Preferably, the non-volatile ferroelectric memory device includes a plurality of cell array blocks, a plurality of sense amplifier units, a plurality of sense amplifier units, a plurality of local data buses, a global data bus, and a plurality of data bus switch arrays. Each of the plurality of cell array blocks has a hierarchical bit line architecture including sub bit lines and a main bit line group corresponding to a plurality of unit cells for storing differential data. The plurality of sense amplifier units, corresponding one-by-one to the cell array blocks, sense and amplify the differential data induced on the main bit line group during a sensing operation. The plurality of local data buses, corresponding one-by-one to the sense amplifier units, transfer the differential data outputted from the sense amplifier units and differential data to be transferred to the sense amplifier units. The global data bus, shared by a plurality of the local data buses, transfers the differential data. The plurality of data bus switch arrays selectively couple the local data buses to the global data bus.

대표청구항 ▼

What is claimed is: 1. A non-volatile ferroelectric memory device comprising: a plurality of cell array blocks each having a hierarchical bit line architecture including a plurality of main bit lines and a plurality of sub bit lines, wherein a voltage of a sub bit line induced by cell data is conve

What is claimed is: 1. A non-volatile ferroelectric memory device comprising: a plurality of cell array blocks each having a hierarchical bit line architecture including a plurality of main bit lines and a plurality of sub bit lines, wherein a voltage of a sub bit line induced by cell data is converted into current so that a sensing voltage of a main bit line is induced, the plurality of cell array blocks including main bit line groups each corresponding to a plurality of unit cells for storing differential data; a plurality of lines connected one by one to the plurality of main bit lines; a plurality of sense amplifier units connected one by one to the plurality of main bit lines through the plurality of lines, for sensing and amplifying the differential data outputted from the main bit line groups in a sensing operation; a plurality of local data buses, corresponding one by one to the plurality of sense amplifier units, for transferring the differential data outputted from the plurality of sense amplifier units and transmitting the differential data inputted to the plurality of sense amplifier units; and a global data bus, shared by the plurality of local data buses, for transferring the differential data, wherein the plurality of sense amplifier units, respectively, comprises: a main bit line sensing load unit for controlling a sensing load of the main bit line groups in response to a load signal; a sense amplifier switch unit, being turned on in read mode in response to a sense amplifier switch signal, for transferring the sensing voltage induced on the main bit line groups; a data latch unit, being activated in response to a sensing control signal, for sensing the sensing voltage on the main bit line groups which is transferred through the sense amplifier switch unit to latch the differential data; a write driving unit, being activated in response to a write control signal in write mode or restore mode, for transferring the differential data stored in the data latch unit to the main bit line groups; and a write selection unit for transferring the differential data applied from the plurality of local data buses to the data latch unit in response to a column selection signal; and a read selection unit for transferring the differential data stored in the data latch unit to the plurality of local data buses in response to the column selection signal. 2. The device according to claim 1, wherein the main bit line groups comprises two adjacent main bit lines. 3. The device according to claim 1, wherein the plurality of sense amplifier units corresponding one-by-one to the main bit line groups comprises a plurality of sense amplifiers for sensing the differential data of the main bit line groups and transferring the sensed differential data to the plurality of local data buses in response to a column selection signal. 4. The device according to claim 1, wherein the write driving unit comprises: a first write driving unit, being activated in response to the write control signal, for transferring a first data of the differential data latched by the data latch unit to a first main bit line of the main bit line groups; and a second write driving unit, being activated in response to the write control signal, for transferring a second data of the differential data latched by the data latch unit to a second main bit line of the main bit line groups.