초록 ▼

Layers of epitaxial silicon are used to protect the tunnel dielectric layer of a floating-gate memory cell from excessive oxidation or removal during the formation of shallow trench isolation (STI) regions. Following trench formation, the layers of epitaxial silicon are grown from silicon-containin

Layers of epitaxial silicon are used to protect the tunnel dielectric layer of a floating-gate memory cell from excessive oxidation or removal during the formation of shallow trench isolation (STI) regions. Following trench formation, the layers of epitaxial silicon are grown from silicon-containing layers on opposing sides of the tunnel dielectric layer, thereby permitting their thickness to be limited to approximately one-half of the thickness of the tunnel dielectric layer. The epitaxial silicon may be oxidized prior to filling the trench with a dielectric material or a dielectric fill may occur prior to oxidizing at least the epitaxial silicon covering the ends of the tunnel dielectric layer.

대표청구항 ▼

What is claimed is: 1. A method of forming an isolation region in an integrated circuit device, comprising: defining an area for the isolation region in a silicon-containing substrate having a dielectric layer overlying the silicon-containing substrate, a silicon-containing layer overlying the diel

What is claimed is: 1. A method of forming an isolation region in an integrated circuit device, comprising: defining an area for the isolation region in a silicon-containing substrate having a dielectric layer overlying the silicon-containing substrate, a silicon-containing layer overlying the dielectric layer and a hard mask layer overlying the silicon-containing layer; removing portions of the hard mask layer, the silicon-containing layer and the dielectric layer from the area for the isolation region, thereby exposing edges of the hard mask layer, silicon-containing layer and dielectric layer; forming a trench in the silicon-containing substrate in the area for the isolation region, thereby exposing sidewalls of the trench; forming layers of epitaxial silicon on the edges of the silicon-containing layer and the exposed sidewalls of the trench; oxidizing the layers of epitaxial silicon after forming the layers of epitaxial silicon; and filling the trench with a dielectric material. 2. The method of claim 1, wherein forming layers of epitaxial silicon further comprises forming layers of epitaxial silicon until the edges of the dielectric layer are covered by epitaxial silicon. 3. The method of claim 1, wherein oxidizing the layers of epitaxial silicon further comprises thermally oxidizing the layers of epitaxial silicon. 4. The method of claim 1, wherein defining an area for the isolation region comprises a photolithographic technique. 5. The method of claim 1, wherein the silicon-containing substrate comprises a monocrystalline silicon substrate. 6. The method of claim 1, wherein the silicon-containing layer comprises a silicon material selected from the group consisting of monocrystalline silicon, amorphous silicon, nanocrystalline silicon and polysilicon. 7. The method of claim 1, further comprising: conductively doping the silicon-containing layer either during or after formation of the silicon-containing layer. 8. A method of forming an isolation region in an integrated circuit device, comprising: defining an area for the isolation region in a silicon-containing substrate having a dielectric layer overlying the silicon-containing substrate, a silicon-containing layer overlying the dielectric layer and a hard mask layer overlying the silicon-containing layer; removing portions of the hard mask layer, silicon-containing layer and dielectric layer from the area for the isolation region, thereby exposing edges of the hard mask layer, silicon-containing layer and dielectric layer; forming a trench in the silicon-containing substrate in the area for the isolation region, thereby exposing sidewalls of the trench; forming layers of epitaxial silicon on the edges of the silicon-containing layer and the exposed sidewalls of the trench; forming a first dielectric fill layer in the trench; removing an upper portion of the first dielectric fill layer from the trench; oxidizing portions of the layers of epitaxial silicon exposed upon removing the upper portion of the first dielectric fill layer; and forming a second dielectric fill layer in the trench. 9. The method of claim 8, wherein forming layers of epitaxial silicon further comprises forming layers of epitaxial silicon until the edges of the dielectric layer are covered by epitaxial silicon. 10. The method of claim 8, wherein oxidizing the layers of epitaxial silicon further comprises thermally oxidizing the layers of epitaxial silicon. 11. The method of claim 8, wherein defining an area for the isolation region comprises a photolithographic technique. 12. A method of forming a floating-gate memory cell, comprising: forming a tunnel dielectric layer overlying a silicon-containing semiconductor substrate; forming a silicon-containing layer overlying the tunnel dielectric layer, the silicon-containing layer forming at least part of a floating-gate layer of the memory cell; forming a hard mask layer overlying the silicon-containing layer; forming a trench through the hard mask layer, silicon-containing layer and tunnel dielectric layer, and into the substrate; growing epitaxial silicon on exposed edges of the silicon-containing layer and on sidewalls of the trench; oxidizing the epitaxial silicon after growing the epitaxial silicon; filling the trench with a dielectric fill material; removing the hard mask layer; forming an intergate dielectric layer overlying the silicon-containing layer; and forming a control gate layer overlying the intergate dielectric layer. 13. The method of claim 12, wherein forming the tunnel dielectric layer further comprises forming a thermally-grown silicon oxide layer on the substrate. 14. The method of claim 12, wherein forming the silicon-containing layer further comprises forming a layer of silicon material selected from the group consisting of monocrystalline silicon, amorphous silicon, nanocrystalline silicon and polysilicon. 15. A method of forming a floating-gate memory cell, comprising: forming a tunnel oxide layer overlying a silicon-containing semiconductor substrate; forming a first polysilicon layer overlying the tunnel oxide layer, the first polysilicon layer forming at least part of a floating-gate layer of the memory cell; forming a hard mask layer overlying the first polysilicon layer; forming a trench through the hard mask layer, first polysilicon layer and tunnel oxide layer, and into the substrate; growing epitaxial silicon on exposed edges of the first polysilicon layer and on sidewalls of the trench; oxidizing the epitaxial silicon after growing the epitaxial silicon; filling the trench with a dielectric fill material; removing the hard mask layer; forming an intergate dielectric layer overlying the first polysilicon layer; and forming a control gate layer overlying the intergate dielectric layer. 16. The method of claim 15, further comprising: forming a second polysilicon layer overlying the first polysilicon layer, the first and second polysilicon layers collectively forming the floating-gate layer. 17. A method of forming a floating-gate memory cell, comprising: forming a tunnel dielectric layer overlying a silicon-containing semiconductor substrate; forming a silicon-containing layer overlying the tunnel dielectric layer, the silicon-containing layer forming at least part of a floating-gate layer of the memory cell; forming a hard mask layer overlying the silicon-containing layer; forming a trench through the hard mask layer, silicon-containing layer and tunnel dielectric layer, and into the substrate; growing epitaxial silicon on exposed edges of the silicon-containing layer and on sidewalls of the trench; filling the trench with a first dielectric fill material; removing an upper portion of the first dielectric fill material, thereby exposing a portion of the epitaxial silicon; oxidizing the exposed portion of the epitaxial silicon; filling the trench with a second dielectric fill material; removing the hard mask layer; forming an intergate dielectric layer overlying the silicon-containing layer; and forming a control gate layer overlying the intergate dielectric layer. 18. A method of forming a floating-gate memory cell, comprising: forming a tunnel oxide layer overlying a silicon-containing semiconductor substrate; forming a first polysilicon layer overlying the tunnel oxide layer, the first polysilicon layer forming at least part of a floating-gate layer of the memory cell; forming a hard mask layer overlying the first polysilicon layer; forming a trench through the hard mask layer, first polysilicon layer and tunnel oxide layer, and into the substrate; growing epitaxial silicon on exposed edges of the first polysilicon layer and on sidewalls of the trench; filling the trench with a first dielectric fill material; removing an upper portion of the first dielectric fill material, thereby exposing a portion of the epitaxial silicon; oxidizing the exposed portion of the epitaxial silicon; filling the trench with a second dielectric fill material; removing the hard mask layer; forming an intergate dielectric layer overlying the first polysilicon layer; and forming a control gate layer overlying the intergate dielectric layer. 19. The method of claim 18, further comprising: forming a second polysilicon layer overlying the first polysilicon layer, the first and second polysilicon layers collectively forming the floating-gate layer.