[특허]Module having stacked chip scale semiconductor packages

[미국특허] Module having stacked chip scale semiconductor packages 원문보기

IPC분류정보
국가/구분	United States(US) Patent 등록
국제특허분류(IPC7판)	H01L-023/02 H01L-021/00 H05K-001/14
출원번호	US-0424480 (2006-06-15)
등록번호	US-7394148 (2008-07-01)
발명자 / 주소	Karnezos,Marcos
출원인 / 주소	Stats Chippac Ltd.
인용정보	피인용 횟수 : 50 인용 특허 : 110

초록 ▼

Stacked CSP (chip scale package) modules include a molded first ("top") chip scale package having a molding side and a substrate side, and a second ("bottom") package affixed to the substrate side of the top chip scale package, the second package being electrically connected to the first package by wire bonding between the first and second package substrates. Also, a method for making a stacked chip scale module includes: providing a first ("top") chip scale package including at least one first package die affixed to and electrically interconnected with a die attach side of a first package substrate, the first CSP being molded and without solder balls; dispensing adhesive on the land side of the first package substrate; providing a singulated second ("bottom") package including at least one second package die affixed to and electrically interconnected with a die attach side of a second package substrate, the second package being molded and without solder balls; affixing the second package onto the land side of the first package substrate, a surface of the molding of the second package contacting the adhesive on the land side of the first package substrate; curing the adhesive; performing a plasma clean; forming wire bond interconnections between the land side of the second package substrate and sites in a marginal area of the land side of the first package substrate; performing a plasma clean; forming a operation to enclose the marginal areas of the land side of the first substrate, the z-interconnection wire bonds and wire loops, the edges of the second package, and the marginal area on the land side of the second package, leaving exposed an area of the land side of the second substrate located within a marginal area; attaching second level interconnect solder balls to sites on the exposed area of the second package substrate; and (where the first substrate was provided in a strip or array) saw singulating to complete a unit assembly.

대표청구항 ▼

What is claimed is: 1. A stacked package module, comprising a module substrate; a first chip scale package mounted on a package attach side of the module substrate, the first chip scale package comprising a first package die attached to a die attach side of a first package substrate and a first package molding having a surface; a land side of a second package is mounted on the surface of the first package molding, wherein electrical interconnection of the first and second packages is made by wire bonds; and a module molding configured so that both the module substrate and a portion of a land side of the first chip scale package substrate are exposed. 2. The module of claim 1 wherein the first chip scale package side of the module comprises a second level interconnect side. 3. The module of claim 1, further comprising second-level interconnection at sites on the exposed portion of the land side of the first package substrate. 4. The module of claim 1, further comprising an additional device mounted on and electrically connected to sites on the module substrate side of the module. 5. The module of claim 4 wherein the additional device comprises a die. 6. The module of claim 4 wherein the additional device comprises a semiconductor package. 7. The module of claim 4 wherein the additional device comprises a passive device. 8. The module of claim 4 wherein the module substrate side of the module comprises a second level interconnect side. 9. The module of claim 1, further comprising second-level interconnection at sites on the land side of the module substrate. 10. The module of claim 9, further comprising an additional device mounted on and electrically connected to sites on the exposed portion of the land side of the first package substrate. 11. The module of claim 10 wherein the additional device comprises a die. 12. The module of claim 11 wherein the additional device comprises a passive device. 13. The module of claim 10 wherein the additional device comprises a semiconductor package.

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Moden Walter L., Flip chip adaptor package for bare die.
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Moden, Walter L., Flip chip adaptor package for bare die.
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Moden, Walter L., Flip chip adaptor package for bare die.
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Lee Shaw Wei (San Jose CA), Maximized substrate design for grid array based assemblies.
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Ball Michael B., Method of fabrication of stacked semiconductor devices.
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Glenn, Thomas P.; Smith, Lee J.; Zoba, David A.; Ramakrishna, Kambhampati; DiCaprio, Vincent, Method of making a semiconductor package including stacked semiconductor dies.
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상세보기
Ichikawa, Sunji, Semiconductor device.
상세보기
Ozawa Kaname,JPX ; Okuda Hayato,JPX ; Hiraoka Tetsuya,JPX ; Sato Mitsutaka,JPX ; Akashi Yuji,JPX ; Okada Akira,JPX ; Harayama Masahiko,JPX, Semiconductor device.
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Tadashi Komiyama JP, Semiconductor device.
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Terui, Makoto, Semiconductor device.
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상세보기
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상세보기
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상세보기
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상세보기
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상세보기
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상세보기
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상세보기
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상세보기
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상세보기
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상세보기
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상세보기
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상세보기
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상세보기
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McMahon, John F., Stacked chip packaging.
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Hoffman, Paul Robert; Zoba, David Albert, Structures for improving heat dissipation in stacked semiconductor packages.
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Rostoker Michael D. (Boulder Creek CA), Techniques for providing high I/O count connections to semiconductor dies.
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Distefano Thomas H., Thermally enhanced packaged semiconductor assemblies.
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Hawke Robert E.,CAX ; Patel Atin J.,CAX ; Binapal Sukhminder S.,CAX ; Divita Charles,CAX ; McNeil Lynn,CAX ; Fletcher Thomas G.,CAX, Three dimensional packaging configuration for multi-chip module assembly.
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더보기 버튼을 클릭하시면 더 많은 관련자료를 살펴볼 수 있습니다.

IPC	Description
A	생활필수품
A62	인명구조; 소방(사다리 E06C)
A62B	인명구조용의 기구, 장치 또는 방법(특히 의료용에 사용되는 밸브 A61M 39/00; 특히 물에서 쓰이는 인명구조 장치 또는 방법 B63C 9/00; 잠수장비 B63C 11/00; 특히 항공기에 쓰는 것, 예. 낙하산, 투출좌석 B64D; 특히 광산에서 쓰이는 구조장치 E21F 11/00)
A62B-1/08	.. 윈치 또는 풀리에 제동기구가 있는 것

내보내기 구분	파일저장 인쇄 메일전송
구성항목	기본정보 상세정보 관리번호, 국가코드, 자료구분, 상태, 출원번호, 출원일자, 공개번호, 공개일자, 등록번호, 등록일자, 발명명칭(한글), 발명명칭(영문), 출원인(한글), 출원인(영문), 출원인코드, 대표IPC 관리번호, 국가코드, 자료구분, 상태, 출원번호, 출원일자, 공개번호, 공개일자, 공고번호, 공고일자, 등록번호, 등록일자, 발명명칭(한글), 발명명칭(영문), 출원인(한글), 출원인(영문), 출원인코드, 대표출원인, 출원인국적, 출원인주소, 발명자, 발명자E, 발명자코드, 발명자주소, 발명자 우편번호, 발명자국적, 대표IPC, IPC코드, 요약, 미국특허분류, 대리인주소, 대리인코드, 대리인(한글), 대리인(영문), 국제공개일자, 국제공개번호, 국제출원일자, 국제출원번호, 우선권, 우선권주장일, 우선권국가, 우선권출원번호, 원출원일자, 원출원번호, 지정국, Citing Patents, Cited Patents
저장형식	Text(ASCII format) Excel format PIAS분석(.xls)
메일정보	받는사람 (필수) @ 보내는사람 (선택) @ 제목 내용 KISTI 검색결과 이메일 서비스
안내	총 건의 자료가 검색되었습니다. 다운받으실 자료의 인덱스를 입력하세요. (1-10,000) 검색결과의 순서대로 최대 10,000건 까지 다운로드가 가능합니다. 데이타가 많을 경우 속도가 느려질 수 있습니다.(최대 2~3분 소요) 다운로드 파일은 UTF-8 형태로 저장됩니다. 파일의 내용이 제대로 보이지 않을실 때는 웹브라우저 상단의 보기 -> 인코딩 -> 자동선택 여부를 확인하십시오. ~ Text(ASCII format) Excel format

연합인증

[미국특허] Module having stacked chip scale semiconductor packages 원문보기

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대표청구항 ▼

연구과제 타임라인

이 특허에 인용된 특허 (110) 인용/피인용 타임라인 분석

이 특허를 인용한 특허 (50) 인용/피인용 타임라인 분석

활용도 분석정보

활용도 Top5 특허

관련 콘텐츠

특허 원문 보기

IPC 상위 출원인

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연합인증

[미국특허] Module having stacked chip scale semiconductor packages 원문보기

초록 ▼

대표청구항 ▼

연구과제 타임라인

전체(0) 논문(0) 특허(0) 보고서(0)

전체(0) 논문(0) 특허(0) 보고서(0)

이 특허에 인용된 특허 (110) 인용/피인용 타임라인 분석

이 특허를 인용한 특허 (50) 인용/피인용 타임라인 분석

활용도 분석정보

활용도 Top5 특허 더보기

관련 콘텐츠

특허 원문 보기

IPC 상위 출원인

AI-Helper ※ AI-Helper는 오픈소스 모델을 사용합니다.

선택된 텍스트

활용도 Top5 특허