초록 ▼

Integrated circuits are provided that have sensitive circuitry such as programmable polysilicon fuses. Electrostatic discharge (ESD) protection circuitry is provided that prevents damage or undesired programming of the sensitive circuitry in the presence of an electrostatic discharge event. The elec

Integrated circuits are provided that have sensitive circuitry such as programmable polysilicon fuses. Electrostatic discharge (ESD) protection circuitry is provided that prevents damage or undesired programming of the sensitive circuitry in the presence of an electrostatic discharge event. The electrostatic discharge protection circuitry may have a power ESD device that limits the voltage level across the sensitive circuitry to a maximum voltage and that draws current away from the sensitive circuitry when exposed to ESD signals. The electrostatic discharge protection circuitry may also have an ESD margin circuit that helps to prevent current flow through the sensitive circuitry when the maximum voltage is applied across the sensitive circuitry.

대표청구항 ▼

What is claimed is: 1. An integrated circuit with electrostatic discharge (ESD) protection circuitry, comprising: a first pin; a second pin; a power ESD device connected between the first pin and the second pin; a conductive line; a control circuit; a plurality of fuses, each of which is connected

What is claimed is: 1. An integrated circuit with electrostatic discharge (ESD) protection circuitry, comprising: a first pin; a second pin; a power ESD device connected between the first pin and the second pin; a conductive line; a control circuit; a plurality of fuses, each of which is connected between the conductive line and the control circuit, wherein the control circuit selectively programs the fuses by selectively connecting the fuses to the first pin; and an ESD margin circuit connected between the second pin and the conductive line that helps to ensure that the power ESD device turns on under ESD conditions and conducts current before any potentially damaging current flows through the fuses. 2. The integrated circuit defined in claim 1 wherein the ESD margin circuit comprises a transistor. 3. The integrated circuit defined in claim 1 wherein the ESD margin circuit comprises a p-channel metal-oxide-semiconductor transistor. 4. The integrated circuit defined in claim 1 wherein the ESD margin circuit comprises a transistor having a first terminal connected to the second pin and a second terminal connected to the conductive line. 5. The integrated circuit defined in claim 1 wherein the ESD margin circuit comprises a transistor having a first terminal connected to the second pin, a second terminal connected to the conductive line, and a third terminal that is biased at a predetermined voltage. 6. The integrated circuit defined in claim 1 wherein the control circuit comprises a plurality of transistors and wherein each of the transistors is connected between a respective one of the fuses and the first pin. 7. The integrated circuit defined in claim 1 wherein the control circuit comprises a plurality of transistors, wherein each of the transistors is connected between a respective one of the fuses and the first pin, and wherein each of the transistors has a gate to which a control signal is applied when it is desired to turn on that transistor and program the fuse that is connected to that transistor. 8. The integrated circuit defined in claim 1 wherein the first pin comprises a ground pin. 9. A method of using an integrated circuit that has electrostatic discharge (ESD) protection circuitry to protect a plurality of fuses on the integrated circuit from damage, wherein the integrated circuit has a first pin, a second pin, a conductive line, a control circuit, and a plurality of fuses each of which is connected between the conductive line and the control circuit, the method comprising: with the control circuit, selectively programming the fuses by selectively connecting the fuses to the first pin; with a power ESD device that is connected between the first pin and the second pin, allowing current to flow in an ESD event to protect the plurality of fuses from damage; and with an ESD margin circuit that is connected in series with the fuses, preventing potentially damaging current from flowing through the fuses by ensuring that the power ESD device turns on under ESD conditions and conducts current before the potentially damaging current flows through the fuses. 10. The method defined in claim 9 wherein the ESD margin circuit comprises a transistor having a first terminal connected to the second pin and a second terminal connected to the conductive line, the method comprising: with the transistor, preventing potentially damaging current from flowing through the fuses under ESD conditions. 11. The method defined in claim 9, wherein the control circuit comprises a plurality of transistors, wherein each of the transistors is connected between a respective one of the fuses and the first pin, and wherein selectively programming the fuses by selectively connecting the fuses to the first pin comprises selectively turning on the transistors.