IPC분류정보
| 국가/구분 |
United States(US) Patent
등록
|
| 국제특허분류(IPC7판) |
|
| 출원번호 |
US-0555603
(2006-11-01)
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| 등록번호 |
US-7403029
(2008-07-22)
|
|
발명자
/ 주소 |
- Chong,Fu Chiung
- Mok,Sammy
|
| 출원인 / 주소 |
|
| 대리인 / 주소 |
|
| 인용정보 |
피인용 횟수 :
8 인용 특허 :
284 |
초록
▼
Several embodiments of massively parallel interface structures are disclosed, which may be used in a wide variety of permanent or temporary applications, such as for interconnecting integrated circuits (ICs) to test and burn-in equipment, for interconnecting modules within electronic devices, for in
Several embodiments of massively parallel interface structures are disclosed, which may be used in a wide variety of permanent or temporary applications, such as for interconnecting integrated circuits (ICs) to test and burn-in equipment, for interconnecting modules within electronic devices, for interconnecting computers and other peripheral devices within a network, or for interconnecting other electronic circuitry. Preferred embodiments of the massively parallel interface structures provide massively parallel integrated circuit test assemblies. The massively parallel interface structures preferably use one or more substrates to establish connections between one or more integrated circuits on a semiconductor wafer, and one or more test modules. One or more layers on the intermediate substrates preferably include MEMS and/or thin-film fabricated spring probes. The parallel interface assemblies provide tight signal pad pitch and compliance, and preferably enable the parallel testing or burn-in of multiple ICs, using commercial wafer probing equipment. In some preferred embodiments, the parallel interface assembly structures include separable standard electrical connector components, which reduces assembly manufacturing cost and manufacturing time. These structures and assemblies enable high speed testing in wafer form.
대표청구항
▼
The invention claimed is: 1. A method of testing at least one semiconductor device on a wafer, comprising the steps of: providing a substrate having a first side and a second side opposite said first side, said substrate further comprising electrical connections extending from said first side to pr
The invention claimed is: 1. A method of testing at least one semiconductor device on a wafer, comprising the steps of: providing a substrate having a first side and a second side opposite said first side, said substrate further comprising electrical connections extending from said first side to probes located on and extending from said second side; providing an interface assembly comprising at least one test electronics module electrically connected to said first side of said substrate, said test electronics modules comprising test electronics; receiving signals at said any of said test electronics modules and said substrate; processing at least one of said received signals within said test electronics at said test electronics modules; and outputting said processed signals to any of said semiconductor device and said test apparatus. 2. The method of claim 1, wherein said test electronics comprise any of passive components, active components, and combinations thereof. 3. The method of claim 1, wherein said test electronics comprise any of a power control module, a decoupling capacitor, a switching control circuit, a regulator, a controller, a pattern generator, a signal measurement circuit, a response detection circuit, a fail detection circuit, means for storing any of pass/fail information, a relay, a switch, means for determining any of a short circuit and an open circuit, means for testing any of a power pin and an I/O pin of said semiconductor device, and means for functional testing of said semiconductor device. 4. The method of claim 1, wherein at least a portion of said test electronics module is disposed substantially coplanar to said substrate. 5. The method of claim 1, wherein said interface assembly further comprises a system board configured between said at least one test electronics module and said substrate. 6. The method of claim 5, wherein said interface assembly further comprises an interposer configured any of or both of between said system board and said substrate and between said test electronics module and said system board. 7. The method of claim 1, wherein said interface assembly comprises a plurality of said test electronics modules. 8. The method of claim 7, wherein at least a portion of said test electronics is disposed on each of said plurality of test electronics modules. 9. The method of claim 8, wherein said test electronics comprise any of passive components, active components, and combinations thereof. 10. The method of claim 8, wherein said test electronics comprise any of a power control module, a decoupling capacitor, a switching control circuit, a regulator, a controller, a pattern generator, a signal measurement circuit, a response detection circuit, a fail detection circuit, means for storing any of pass/fail information, a relay, a switch, means for determining any of a short circuit and an open circuit, means for testing any of a power pin and an I/O pin of said semiconductor device, and means for functional testing of said semiconductor device. 11. The method of claim 8, wherein said test electronics on at least one of said plurality of test electronics modules process at least a portion of said signals for testing one or more of said semiconductor devices. 12. The method of claim 11, wherein at least a portion of said signals comprise response signals generated by at least one of said semiconductor devices, and wherein said test electronics on at least one of said plurality of test electronics modules process at least a portion of said generated response signals. 13. The method of claim 11, wherein at least a portion of said signals are test signals generated by said test apparatus, and wherein said test electronics on at least one of said plurality of test electronics modules process at least a portion of said generated test signals. 14. The method of claim 7, wherein each of said plurality of test electronics modules are disposed parallel to each other. 15. The method of claim 1, wherein said test electronics process at least a portion of said signals for testing of said semiconductor device. 16. The method of claim 15, wherein at least a portion of said signals comprise response signals generated by said semiconductor device, and wherein said test electronics process at least a portion of said generated response signals. 17. The method of claim 15, wherein at least a portion of said signals are test signals generated by said test apparatus, and wherein said test electronics process at least a portion of said generated test signals. 18. A probe card assembly, comprising: a substrate having a first side and a second side opposite said first side, said substrate further comprising electrical connections extending from said first side to probes located on and extending from said second side for electrically contacting at least one semiconductor device; an interface assembly comprising at least one test electronics module electrically connected to said first side of said substrate; means for electrically connecting a test apparatus to any of said interface assembly and at least one of said connections on said first side of said substrate; and test electronics, at least a portion of which are disposed on said test electronics module; wherein said test electronics receive as input signals received from any of said test apparatus and said semiconductor device, process said received signals there within, and output said processed received signals. 19. The probe card assembly of claim 18, wherein said test electronics comprise any of passive components, active components, and combinations thereof. 20. The probe card assembly of claim 18, wherein said test electronics comprise any of a power control module, a decoupling capacitor, a switching control circuit, a regulator, a controller, a pattern generator, a signal measurement circuit, a response detection circuit, a fail detection circuit, means for storing any of pass/fail information, a relay, a switch, means for determining any of a short circuit and an open circuit, means for testing any of a power pin and an I/O pin of said semiconductor device, and means for functional testing of said semiconductor device. 21. The probe card assembly of claim 18, further comprising: a system board configured between said at least one test electronics module and said substrate. 22. The probe card assembly of claim 21, further comprising: an interposer configured any of or both of between said system board and said substrate and between said test electronics module and said system board. 23. A method of making a probe card assembly, comprising the steps of: providing a substrate having a first side and a second side opposite said first side, said substrate further comprising a plurality of contacts on said first side and electrical connections extending from said first side to probes located on and extending from said second side for electrically contacting at least one semiconductor device; providing an interface assembly comprising at least one test electronics module electrically connected to said first side of said substrate; and providing test electronics that receive as input signals received from any of said test apparatus and said semiconductor device, process said received signals there within, and output said processed received signals; wherein at least a portion of said test electronics are located on said test electronics module. 24. The method of claim 23, wherein said test electronics comprise any of passive components, active components, and combinations thereof. 25. The method of claim 23, wherein said test electronics comprise any of a power control module, a decoupling capacitor, a switching control circuit, a regulator, a controller, a pattern generator, a signal measurement circuit, a response detection circuit, a fail detection circuit, means for storing any of pass/fail information, a relay, a switch, means for determining any of a short circuit and an open circuit, means for testing any of a power pin and an I/O pin of said semiconductor device, and means for functional testing of said semiconductor device. 26. The method of claim 23, wherein said interface assembly further comprises a system board configured between said at least one test electronics module and said substrate. 27. The method of claim 26, wherein said interface assembly further comprises an interposer configured any of or both of between said system board and said substrate and between said test electronics module and said system board.
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