초록 ▼

A motor drive system control provides global closed loop feedback to cooperatively operate system components to adaptively reduce noise and provide noise cancellation feedback. An active EMI filter reduces differential and common mode noise on an input and provides a noise level indication to a syst

A motor drive system control provides global closed loop feedback to cooperatively operate system components to adaptively reduce noise and provide noise cancellation feedback. An active EMI filter reduces differential and common mode noise on an input and provides a noise level indication to a system controller. Power switches in both a power converter and power inverter are cooperatively controlled with dynamic dv/dt control to reduce switching noise according to a profile specified by the controller. The dv/dt control is provided as an analog signal to a high voltage IC and codified as a pulse width for a level shifting circuit supplying control signals to the high voltage gate drive. A noise extraction circuit and technique obtain fast noise sampling to permit noise cancellation and adaptive noise reduction.

대표청구항 ▼

What is claimed is: 1. An integrated circuit for supplying gate command signals to a high-side power switch, comprising: a gate drive circuit for applying turn on and turn off signals to the power switch; a command input circuit for providing set reset pulses to operate the gate drive circuit by pr

What is claimed is: 1. An integrated circuit for supplying gate command signals to a high-side power switch, comprising: a gate drive circuit for applying turn on and turn off signals to the power switch; a command input circuit for providing set reset pulses to operate the gate drive circuit by processing input control pulses for controlling the high-side power switch and a rate of voltage change per unit time signal for controlling the gate drive circuit to produce a specified voltage applied to a gate of the high-side power switch during turn on or turn off times; and a gate voltage control circuit for converting the set and reset pulses to a voltage signal to control the gate drive circuit by varying the high-side power switch turn on and turn off time based on the voltage signal, wherein the set and reset pulses indicate a length of the input control pulses supplied to the high-side power switch, further comprising: a level shifting circuit coupled to the command input circuit for shifting a voltage level of the set and reset pulses. 2. The integrated circuit according to claim 1, further comprising: a second gate drive circuit for providing an output to control a gate of a low power switch; and a second gate command input pulse to control the second gate drive circuit; a second rate of voltage change per unit time signal input coupled to the second gate drive circuit for controlling a rate of voltage change per unit time for the output provided by the low gate drive circuit. 3. A method for controlling a motor drive system to reduce noise, the motor drive system including at least one pair of high-and low-side power switches having gate terminals and connected between a DC voltage line and a voltage line return, the method comprising the steps of: receiving input control pulses for control of the high-and low-side power switches; providing rate signals related to a desired rate of change of voltage per unit time for controlling the gates of the high-and low-side power switches in the motor drive system; generating set and reset pulses for indicating a length of the input control pulses supplied to the high-side power switch; applying the set and reset pulses to a gate driver circuit for the high-side power switch; converting the set and reset pulses to a voltage signal to control the gate drive circuit by varying the high-side power switch turn on and turn off time based on the voltage signal; and modifying the rate signals based on an adaptive trade off between noise reduction and switching losses in the high-side power switch by changing one of turn on and turn off times of the power switch. 4. The method according to claim 3, further comprising applying a slow voltage rate of change per unit time to turn on the power switch to reduce differential mode noise. 5. The method according to claim 3, further comprising applying a slow voltage rate of change per unit time to turn on and turn off the power switch to reduce common mode noise. 6. The method of claim 3, wherein the input control pulses are configured and timed so that the high-and low-side switches are not on at the same time, the high-and low-side switches being permitted to be off at the same time. 7. The method of claim 3, wherein the step of generating set and reset pulses is achieved by processing the input control pulses and the rate of change signals for the high side gate drive, the rate of change signals conditioning the input control pulses to be transmitted at a specified rate of change over time for the voltage applied to the high-side switch. 8. The method of claim 7, further comprising a step of level shifting the set and reset pulses referenced to any input potential between the DC voltage line and voltage line return for the high-side switch to obtain an appropriate control voltage referenced to a high side logic ground reference, wherein the level shifting prevents loss of signal to the high side power switch and avoids voltage swings with values less than a fixed ground reference. 9. The method of claim 8, further comprising a step of filtering the level shifted pulses to induce a delay in a flip-flop circuit. 10. The method of claim 9, further comprising a step of supplying an upward transition to a gate drive circuit delivering a high logic signal for the same duration of time as indicated by the input control pulses when the flip flop circuit is set ON and causing a high to low transition to gate drive circuit ending the interval for a switch ON time at the end of duration of the input control pulse and resetting the flip flop circuit.