초록 ▼

An electro-optical device comprising a display drive system with the display timing related to the unit time t for writing-in a picture element and to the time F for writing-in one picture is disclosed. In the device, a gradated display corresponding to the ratio of the division can be obtained by

An electro-optical device comprising a display drive system with the display timing related to the unit time t for writing-in a picture element and to the time F for writing-in one picture is disclosed. In the device, a gradated display corresponding to the ratio of the division can be obtained by time-sharing the signal during a write-in of time t without changing the time F.

대표청구항 ▼

What is claimed is: 1. A method of manufacturing an active matrix type display device comprising the steps of: forming a gate electrode over an insulating surface of a first substrate; forming a gate insulating film over said gate electrode; depositing an amorphous semiconductor film comprising sil

What is claimed is: 1. A method of manufacturing an active matrix type display device comprising the steps of: forming a gate electrode over an insulating surface of a first substrate; forming a gate insulating film over said gate electrode; depositing an amorphous semiconductor film comprising silicon on said gate insulating film; patterning said semiconductor film into an island comprising a channel region; forming a first organic leveling film over said semiconductor film after said patterning thereof to provide a leveled upper surface; forming an opening in said organic leveling film; forming a pixel electrode over said organic leveling film through said opening; forming a resin black matrix over a second substrate; forming a second organic leveling film over said resin black matrix; forming a counter electrode on said second leveling film; and facing said second substrate to said first substrate so that said counter electrode and said pixel electrode are opposed to each other. 2. A method according to claim 1 further comprising a step of depositing an n-type semiconductor layer on said amorphous semiconductor film through plasma CVD using a mixture gas containing a silane, phosphine and hydrogen. 3. A method according to claim 1 further comprising a step of forming a pair of impurity doped semiconductor layers on said island, wherein one of said impurity doped semiconductor layers is electrically connected with said pixel electrode. 4. A method according to claim 1 wherein said gate electrode comprises a doped silicon film and a molybdenum film formed thereon. 5. A method according to claim 1 wherein said gate electrode comprises aluminum. 6. A method according to claim 1 wherein said gate insulating film comprises silicon oxide. 7. A method according to claim 1 wherein said amorphous semiconductor film is deposited through plasma CVD. 8. A method according to claim 1 wherein said amorphous semiconductor film is deposited to a thickness of 500 to 5000 Å. 9. A method according to claim 1 wherein said organic leveling film directly contacts a portion of said amorphous semiconductor film. 10. A method according to claim 1 wherein said pixel electrode extends over said channel region. 11. A method of manufacturing an active matrix type display device comprising the steps of: forming a gate electrode over an insulating surface of a first substrate; forming a gate insulating film over said gate electrode; depositing an amorphous semiconductor film comprising silicon on said gate insulating film; patterning said semiconductor film into an island comprising a channel region; forming a first organic leveling film over said semiconductor film after said patterning thereof to provide a leveled upper surface; forming an opening in said organic leveling film; forming a pixel electrode over said organic leveling film through said opening; forming a color filter over a second substrate; forming a resin black matrix over said second substrate; forming a second organic leveling film over said color filter and said resin black matrix; forming a counter electrode on said second leveling film; and facing said second substrate to said first substrate so that said counter electrode and said pixel electrode are opposed to each other. 12. A method according to claim 11 further comprising a step of depositing an n-type semiconductor layer on said amorphous semiconductor film through plasma CVD using a mixture gas containing a silane, phosphine and hydrogen. 13. A method according to claim 11 further comprising a step of forming a pair of impurity doped semiconductor layers on said island, wherein one of said impurity doped semiconductor layers is electrically connected with said pixel electrode. 14. A method according to claim 11 wherein said gate electrode comprises a doped silicon film and a molybdenum film formed thereon. 15. A method according to claim 11 wherein said gate electrode comprises aluminum. 16. A method according to claim 11 wherein said gate insulating film comprises silicon oxide. 17. A method according to claim 11 wherein said amorphous semiconductor film is deposited through plasma CVD. 18. A method according to claim 11 wherein said amorphous semiconductor film is deposited to a thickness of 500 to 5000 Å. 19. A method according to claim 11 wherein said organic leveling film directly contacts a portion of said amorphous semiconductor film. 20. A method according to claim 11 wherein said pixel electrode extends over said channel region. 21. A method of manufacturing an active matrix type display device comprising the steps of: forming a gate electrode over an insulating surface of a first substrate; forming a gate insulating film over said gate electrode; depositing an amorphous semiconductor film comprising silicon on said gate insulating film; patterning said semiconductor film into an island comprising a channel region; forming a first organic leveling film over said semiconductor film after said patterning thereof to provide a leveled upper surface; forming an opening in said organic leveling film; forming a pixel electrode over said organic leveling film through said opening; forming a resin black matrix over a second substrate; forming a second organic leveling film over said resin black matrix; forming a counter electrode on said second leveling film; and facing said second substrate to said first substrate so that said counter electrode and said pixel electrode are opposed to each other, wherein said opening has a tapered configuration so that a diameter thereof is larger at an upper portion than at a lower portion of said opening, and wherein said upper portion of said opening is rounded from a first point on said leveled upper surface of said leveling film to a second point inside said opening adjacent said upper portion. 22. A method according to claim 21 further comprising a step of depositing an n-type semiconductor layer on said amorphous semiconductor film through plasma CVD using a mixture gas containing a silane, phosphine and hydrogen. 23. A method according to claim 21 further comprising a step of forming a pair of impurity doped semiconductor layers on said island, wherein one of said impurity doped semiconductor layers is electrically connected with said pixel electrode. 24. A method according to claim 21 wherein said gate electrode comprises a doped silicon film and a molybdenum film formed thereon. 25. A method according to claim 21 wherein said gate electrode comprises aluminum. 26. A method according to claim 21 wherein said gate insulating film comprises silicon oxide. 27. A method according to claim 21 wherein said amorphous semiconductor film is deposited through plasma CVD. 28. A method according to claim 21 wherein said amorphous semiconductor film is deposited to a thickness of 500 to 5000 Å. 29. A method according to claim 21 wherein said organic leveling film directly contacts a portion of said amorphous semiconductor film. 30. A method according to claim 21 wherein said pixel electrode extends over said channel region. 31. A method of manufacturing an active matrix type display device comprising the steps of: forming a gate electrode over an insulating surface of a first substrate; forming a gate insulating film over said gate electrode; depositing an amorphous semiconductor film comprising silicon on said gate insulating film; patterning said semiconductor film into an island comprising a channel region; forming a first organic leveling film over said semiconductor film after said patterning thereof to provide a leveled upper surface; forming an opening in said organic leveling film; forming a pixel electrode over said organic leveling film through said opening; forming a color filter over a second substrate; forming a resin black matrix over said second substrate; forming a second organic leveling film over said color filter and said resin black matrix; forming a counter electrode on said second leveling film; and facing said second substrate to said first substrate so that said counter electrode and said pixel electrode are opposed to each other, wherein said opening has a tapered configuration so that a diameter thereof is larger at an upper portion than at a lower portion of said opening, and wherein said upper portion of said opening is rounded from a first point on said leveled upper surface of said leveling film to a second point inside said opening adjacent said upper portion. 32. A method according to claim 31 further comprising a step of depositing an n-type semiconductor layer on said amorphous semiconductor film through plasma CVD using a mixture gas containing a silane, phosphine and hydrogen. 33. A method according to claim 31 further comprising a step of forming a pair of impurity doped semiconductor layers on said island, wherein one of said impurity doped semiconductor layers is electrically connected with said pixel electrode. 34. A method according to claim 31 wherein said gate electrode comprises a doped silicon film and a molybdenum film formed thereon. 35. A method according to claim 31 wherein said gate electrode comprises aluminum. 36. A method according to claim 31 wherein said gate insulating film comprises silicon oxide. 37. A method according to claim 31 wherein said amorphous semiconductor film is deposited through plasma CVD. 38. A method according to claim 31 wherein said amorphous semiconductor film is deposited to a thickness of 500 to 5000 Å. 39. A method according to claim 31 wherein said organic leveling film directly contacts a portion of said amorphous semiconductor film. 40. A method according to claim 31 wherein said pixel electrode extends over said channel region.