[미국특허]
Three inch silicon carbide wafer with low warp, bow, and TTV
원문보기
IPC분류정보
국가/구분
United States(US) Patent
등록
국제특허분류(IPC7판)
C01B-033/20
C01B-033/00
C30B-023/00
출원번호
US-0101110
(2005-04-07)
등록번호
US-7422634
(2008-09-09)
발명자
/ 주소
Powell,Adrian
Brixius,William H.
Leonard,Robert Tyler
McClure,Davis Andrew
Laughner,Michael
출원인 / 주소
Cree, Inc.
대리인 / 주소
Summa, Allan & Addition, P.A.
인용정보
피인용 횟수 :
33인용 특허 :
56
초록
A high quality single crystal wafer of SiC is disclosed. The wafer has a diameter of at least about 3 inches, a warp of less than about 5 μm, a bow less than about 5 μm, and a total thickness variation of less than about 2.0 μm.
대표청구항▼
The invention claimed is: 1. A high quality single crystal wafer of SiC having a diameter of at least about 3 inches, a warp of less than about 5 μm, a bow of less than about 5 μm and a TTV of less than about 2.0 μm. 2. A SiC crystal according to claim 1 wherein the warp is less th
The invention claimed is: 1. A high quality single crystal wafer of SiC having a diameter of at least about 3 inches, a warp of less than about 5 μm, a bow of less than about 5 μm and a TTV of less than about 2.0 μm. 2. A SiC crystal according to claim 1 wherein the warp is less than about 2 μm. 3. A SiC crystal according to claim 1 wherein the warp is less than about 1 μm. 4. A SiC crystal according to claim 1 wherein the bow is less than about 2 μm. 5. A SiC crystal according to claim 1 wherein the bow is less than about 1 μm. 6. A SiC crystal according to claim 1 wherein the TTV is less than about 1.5 μm. 7. A SiC crystal according to claim 1 wherein the TTV is less than about 1 μm. 8. A SiC crystal according to claim 1 wherein the crystal has a polytype selected from the group consisting of the 3C, 4H, 6H, 2H, and 15R polytypes. 9. A high quality semiconductor wafer comprising: a silicon carbide wafer having a diameter of at least about 3 inches; said wafer having the 4H polytype; and said wafer having a warp of between about 0.05 μm and about 5 μm, a bow of between about 0.05 μm and about 5 μm, and a TTV of between about 0.5 and 2.0 μm. 10. A high quality semiconductor precursor wafer comprising: a silicon carbide wafer having a diameter of at least about 3 inches; said wafer having a warp of less than about 5 μm, a bow of less than about 5 μm, and a TTV of less than about 2.0 μm; and at least one epitaxial layer on said surface of said silicon carbide wafer selected from the group consisting of Group III-nitrides and silicon carbide. 11. A semiconductor wafer according to claim 10 wherein said Group III-nitride layer is selected from the group consisting of GaN, AlGaN, AlN, AlInGaN, InN, AlInN, and combinations thereof. 12. A semiconductor device precursor structure comprising: a silicon carbide wafer having a diameter of at least about 3 inches, a warp of less than about 5 μm, a bow of less than about 5 μm, and a TTV of less than about 2.0 μm; and a plurality of respective Group III-nitride epitaxial layers on some portions of said wafer. 13. A semiconductor wafer comprising: a bulk single crystal silicon carbide substrate having a diameter of at least about 3 inches, a warp of less than about 5 μm, a bow of less than about 5 μm, and a TTV of less than about 2.0 μm, said bulk single crystal having respective first and second surfaces opposite one another; and a plurality of devices on said silicon carbide substrate, each said device comprising: an epitaxial layer located on the substrate, said layer having a concentration of suitable dopant atoms for making the epitaxial layer a first conductivity type, and respective source, channel, and drain portions; a metal oxide layer on said channel portion; and a metal gate contact on said metal oxide layer for forming an active channel when a bias is applied to said metal gate contact. 14. A semiconductor wafer comprising: a bulk single crystal silicon carbide substrate having a diameter of at least about 3 inches, a warp of less than about 5 μm, a bow of less than about 5 μm, a TTV of less than about 2.0 μm, said bulk single crystal having respective first and second surfaces opposite one another; and a plurality of devices on said silicon carbide substrate, each said device comprising: a conductive channel on said substrate; a source and a drain on said conductive channel; and a metal gate contact between said source and said drain on said conductive channel for forming an active channel when a bias is applied to said metal gate contact. 15. A semiconductor wafer comprising: a bulk single crystal silicon carbide substrate having a diameter of at least about 3 inches, a warp of less than about 5 μm, a bow of less than about 5 μm, and a TTV of less than about 2.0 μm, said bulk single crystal having respective first and second surfaces opposite one another; and a plurality of junction field-effect transistors positioned on said single crystal silicon carbide substrate. 16. A semiconductor wafer comprising: a bulk single crystal silicon carbide substrate having a diameter of at least about 3 inches, a warp of less than about 5 μm, a bow of less than about 5 μm, and a TTV of less than about 2.0 μm, said bulk single crystal having respective first and second surfaces opposite one another; and a plurality of hetero-field effect transistors positioned on said single crystal silicon carbide substrate. 17. A semiconductor wafer comprising: a bulk single crystal silicon carbide substrate having a diameter of at least about 3 inches, a warp of less than about 5 μm, a bow of less than about 5 μm, and a TTV of less than about 2.0 μm, said bulk single crystal having respective first and second surfaces opposite one another; and a plurality of diodes positioned on said single crystal silicon carbide substrate.
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