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A flat display device may include a plurality of electrodes arranged in one direction, a first transistor coupled between the plurality of electrodes and a first power source for supplying a first voltage, and a gate driving circuit for supplying a driving voltage to a gate of the first transistor t

A flat display device may include a plurality of electrodes arranged in one direction, a first transistor coupled between the plurality of electrodes and a first power source for supplying a first voltage, and a gate driving circuit for supplying a driving voltage to a gate of the first transistor through a push-pull circuit including second and third transistors coupled between second and third power sources for respectively supplying second and third power sources, wherein a resistance formed between the second transistor and the second power source is greater than that formed between the third transistor and the third power source.

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What is claimed is: 1. A flat display device, comprising a plurality of electrodes arranged in one direction; a first transistor coupled between the plurality of electrodes and a first power source for supplying a first voltage; and a gate driving circuit for supplying a driving voltage to a gate o

What is claimed is: 1. A flat display device, comprising a plurality of electrodes arranged in one direction; a first transistor coupled between the plurality of electrodes and a first power source for supplying a first voltage; and a gate driving circuit for supplying a driving voltage to a gate of the first transistor through a push-pull circuit including second and third transistors coupled between second and third power sources for respectively supplying second and third power voltages; wherein a resistance between the second transistor and the second power source is greater than that between the third transistor and the third power source. 2. The flat display device as claimed in claim 1, wherein one of the second and third transistors is an NPN transistor and the other of the second and third transistors is a PNP transistor. 3. The flat display device as claimed in claim 1, further comprising a first resistor between the second power source and a collector of the second transistor. 4. The flat display device as claimed in claim 1, wherein a time for changing a voltage between the gate and a source of the first transistor from a fourth voltage corresponding to the third voltage to a fifth voltage corresponding to the second voltage in response to a turn-on of the second transistor is longer than that for changing a voltage between the gate and source of the first transistor from the fifth voltage to the fourth voltage corresponding to the second voltage in response to a turn-on of the third transistor. 5. The flat display device as claimed in claim 2, wherein a control signal having a first voltage level or a second voltage level is applied to bases of the second and third transistors; the second transistor is turned on in response to a first voltage level of the control signal, and the third transistor is turned on in response to a second voltage level of the control signal, the first voltage level being different from the second voltage level; and emitters of the second and third transistors are coupled to an output terminal of the push-pull circuit. 6. The flat display device as claimed in claim 5, wherein the second transistor is the NPN transistor, the third transistor is the PNP transistor, and the first voltage level is greater than the second voltage level. 7. The flat display device as claimed in claim 5, further comprising a capacitor coupled between the output terminal of the push-pull circuit and the gate and source of the first transistor. 8. The flat display device as claimed in claim 7, further comprising: a second resistor coupled between the first power source and a first terminal of the capacitor; a third resistor coupled between a second terminal of the capacitor and the gate of the first transistor; a fourth resistor coupled between the second terminal of the capacitor and a source of the first transistor; and a zener diode coupled between the second terminal of the capacitor and the source of the first transistor. 9. The flat display device as claimed in claim 5, further comprising a capacitor having a first terminal for supplying the second voltage of the second power source and a second terminal for supplying the third voltage of the third power source, and charged with a voltage corresponding to a difference between the second and third voltages, the second terminal being coupled to the source of the first transistor. 10. The flat display device as claimed in claim 9, further comprising a diode coupled between the first terminal of the capacitor and the first resistor. 11. The flat display device as claimed in claim 10, further comprising a second resistor coupled between the gate of the first transistor and the output terminal of the push-pull circuit. 12. A gate driving device for driving a gate of a driving transistor, the gate driving device comprising: a first transistor having an emitter coupled to an output terminal of the gate driving device; a first resistor coupled between a first power source for supplying a first voltage and a collector of the first transistor; a second transistor of a different conductive type from the first transistor, having an emitter coupled to the output terminal and a collector coupled to a second power source for supplying a second voltage; and a second resistor coupled between the collector of the second transistor and the second power source, wherein a resistance of the first resistor is greater than a resistance of the second resistor, and wherein a gate of the driving transistor is applied with a voltage corresponding to a voltage of the output terminal in response to a control signal applied to bases of the first and second transistors. 13. The gate driving apparatus as claimed in claim 12, wherein the control signal has a first voltage level or a second voltage level, the first transistor is turned on in response to the first voltage level, and the second transistor is turned on in response to the second voltage level, the first voltage level being different from the second voltage level. 14. The gate driving apparatus as claimed in claim 13, further comprising a capacitor coupled between the output terminal and the gate of the driving transistor. 15. The gate driving apparatus as claimed in claim 13, further comprising a capacitor having a first terminal for supplying a first voltage of the first power source and a second terminal for supplying a second voltage of the second power source, and charged by a voltage corresponding to a difference between the first and second voltages, the second terminal being coupled to a source of the first transistor. 16. The gate driving apparatus as claimed in claim 13, wherein the first transistor is a NPN transistor and the second transistor is a PNP transistor. 17. A driving circuit for a flat panel display apparatus including a plurality of electrodes arranged in one direction, a first transistor coupled between the plurality of electrodes and a first power source for supplying a first voltage, the driving circuit for driving the first transistor, the driving circuit comprising: a push-pull circuit including second and third transistors coupled between second and third power sources for respectively supplying second and third power sources; and delaying means for delaying a start time for supplying a turn-on voltage signal for turning on the first transistor relative to a start time for supplying a turn-off signal for turning off the first transistor. 18. The driving circuit as claimed in claim 17, wherein the delaying means includes resistance means between at least one of the second transistor and the second power source and the third transistor and the third power source such that a resistance between the second transistor and the second power source is greater than a resistance between the third transistor and the third power source. 19. The driving circuit as claimed in claim 17, wherein the second and third transistors are coupled at an output terminal of the push-pull circuit, and the delaying means includes resistance means between the output terminal of the push-pull circuit and the second transistor.