[특허]Methods, circuits, architectures, software and systems for determining a data transmission error and/or checking or confirming such error determinations

Marvell Israel (M.I.S.L.)  Ltd.

검색어에 아래의 연산자를 사용하시면 더 정확한 검색결과를 얻을 수 있습니다.
검색연산자

검색도움말
검색연산자	기능	검색시 예
()	우선순위가 가장 높은 연산자	예1) (나노 (기계 \| machine))
공백	두 개의 검색어(식)을 모두 포함하고 있는 문서 검색	예1) (나노 기계) 예2) 나노 장영실
\|	두 개의 검색어(식) 중 하나 이상 포함하고 있는 문서 검색	예1) (줄기세포 \| 면역) 예2) 줄기세포 \| 장영실
!	NOT 이후에 있는 검색어가 포함된 문서는 제외	예1) (황금 !백금) 예2) !image
*	검색어의 *란에 0개 이상의 임의의 문자가 포함된 문서 검색	예) semi*
""	따옴표 내의 구문과 완전히 일치하는 문서만 검색	예) "Transform and Quantization"

과학기술 지식인프라 ScienceON

연합인증

연합인증 가입 기관의 연구자들은 소속기관의 인증정보(ID와 암호)를 이용해 다른 대학, 연구기관, 서비스 공급자의 다양한 온라인 자원과 연구 데이터를 이용할 수 있습니다.

이는 여행자가 자국에서 발행 받은 여권으로 세계 각국을 자유롭게 여행할 수 있는 것과 같습니다.

연합인증으로 이용이 가능한 서비스는 NTIS, DataON, Edison 등이 있습니다.

한번의 인증절차만으로 연합인증 가입 서비스에 추가 로그인 없이 이용이 가능합니다.

다만, 연합인증을 위해서는 최초 1회만 인증 절차가 필요합니다. (회원이 아닐 경우 회원 가입이 필요합니다.)

연합인증 절차는 다음과 같습니다.

최초이용시에는
ScienceON에 로그인 → 연합인증 서비스 접속 → 로그인 (본인 확인 또는 회원가입) → 서비스 이용

그 이후에는
ScienceON 로그인 → 연합인증 서비스 접속 → 서비스 이용

연합인증을 활용하시면 KISTI가 제공하는 다양한 서비스를 편리하게 이용하실 수 있습니다.

특허 상세정보

MyON담기

내보내기 페이스북 공유 트위터 공유 카카오톡 공유

Methods, circuits, architectures, software and systems for determining a data transmission error and/or checking or confirming such error determinations

특허상세정보
국가/구분	United States(US) Patent 등록
국제특허분류(IPC7판)	H03M-013/09 H03M-013/00
미국특허분류(USC)	714/807
출원번호	US-0795003 (2004-03-03)
등록번호	US-7434150 (2008-10-07)
발명자 / 주소	Barash,Dror
출원인 / 주소	Marvell Israel (M.I.S.L.) Ltd.
인용정보	피인용 횟수 : 13 인용 특허 : 46

초록
▼

Methods, circuits, architectures, and systems for error detection in transmitted data. The method generally includes the steps of (a) performing an error checking calculation on the transmitted data and appended error checking code; (b) determining the calculated error checking code state; and (c) if it has a predetermined state, indicating that there is no error in the transmitted data. The circuitry generally comprises (1) an error checking code calculation circuit configured to calculate error checking code on the transmitted data and the appended error checking code; (2) a vector selector configured to select one of a plurality of error checking vectors; and (3) a logic circuit configured to determine the calculated error checking code state and, if it has a predetermined state, indicate that there is no error in the transmitted data. The software generally includes a set of instructions configured to implement or carry out the present method. The architectures and/or systems generally include those that embody one or more of the inventive concepts disclosed herein. In the present invention, an error checking calculation is performed on error checking code transmitted with the data. If the transmitted data and error checking code are error-free, the error checking calculation gives a result having a known and/or predetermined state. This technique enables one to confirm or determine that the data transmission was error-free without use of or need for a wide, complicated comparator, thereby reducing the chip area dedicated to error detection, increasing the utilization efficiency of the circuitry on the chip, and reducing power consumption.

대표
청구항
▼

What is claimed is: 1. A method of determining or confirming an error in transmitted data, comprising the steps of: a) receiving said transmitted data and then partitioning said received data into at least one data line and a last line, each of said at least one data line and said last line having a first fixed length, and the last line containing appended error checking code calculated on said transmitted data; b) when said partitioned received data has a remainder, said remainder having any length less than said first fixed length and greater than zero, appending a pad vector to said remainder, the pad vector having a length sufficient to form a first data line with said first fixed length when the pad vector is appended to said remainder; c) performing an error checking calculation on said first line, said at least one data line and any data in said last line to generate an error checking vector; d) iterating the error checking calculation on said appended error checking code using said error checking vector to provide a calculated error checking result; e) determining a state of said calculated error checking result; and f) if said calculated error checking result has a predetermined state, indicating that there is no error in said transmitted data. 2. The method of claim 1, wherein said one or more data lines each comprise a plurality of data blocks, each data block having a second fixed length, said second fixed length being an integer divisor of said first fixed length, and said appended error checking code has a third length comprising an integer multiple of said second fixed length, said integer multiple being the same as or less than said integer divisor. 3. The method of claim 1, wherein said first fixed length comprises 2m bits, where m is an integer of from 6 to 10. 4. The method of claim 1, wherein said step of performing an error checking calculation comprises checking each of said first line, said at least one data line and said last line with common error checking circuitry. 5. The method of claim 1, wherein said predetermined state is selected from the group consisting of all zeros and all ones. 6. The method of claim 1, wherein if said calculated error checking result does not have said predetermined state, indicating that there is an error in said transmitted data. 7. The method of claim 1, wherein said appended error checking code has a length of p bits, where p is an integer of from 8 to 128. 8. The method of claim 7, wherein p is 8, 16, 32, 64 or 128. 9. The method of claim 1, wherein performing said error checking calculation on said first line, said at least one data line and any data in said last line comprises a plurality of cyclic redundancy check (CRC) calculations. 10. The method of claim 9, wherein said appended error checking code comprises a CRC calculation result on said transmitted data. 11. The method of claim 9, wherein iterating the error checking calculation on said appended error checking code comprises a CRC calculation on said appended error checking code. 12. A computer-readable medium containing a set of instructions which, when executed by a signal processing device configured to execute computer-readable instructions, is configured to cause a receiver circuit to perform the method of claim 1. 13. The computer-readable medium of claim 12, wherein said transmitted error checking code has a length of p bits, where p is an integer of from 8 to 128. 14. The computer-readable medium of claim 12, wherein said fixed length comprises 2m bits, where m is an integer of from 6 to 10. 15. The computer-readable medium of claim 12, wherein said error checking calculations comprise cyclic redundancy check (CRC) calculations. 16. The computer-readable medium of claim 12, wherein said predetermined state is selected from the group consisting of all zeros and all ones. 17. The computer-readable medium of claim 12, wherein said set of instructions further comprises an instruction to indicate that there is an error in said transmitted data if said calculated error checking result does not have said predetermined state. 18. The computer-readable medium of claim 12, wherein said set of instructions further comprises an instruction to select the pad vector from a set of padding vectors. 19. The computer-readable medium of claim 18, wherein said pad vector is a zero-pad vector. 20. The computer-readable medium of claim 12, wherein said set of instructions further comprises an instruction to determine a length of said remainder. 21. The computer-readable medium of claim 20, wherein said pad vector is selected in response to information comprising said length of said remainder. 22. A circuit for determining a data transmission error and/or checking a data transmission error determination, comprising: a) a data partitioning circuit configured to receive transmitted data and an appended error checking code calculated on said transmitted data, and then partition said transmitted data and said appended error checking code into at least one data line having a first fixed length and a last line comprising said appended error checking code and having said first fixed length; b) an error checking code calculation circuit configured to perform error checking calculations on a first data line, said at least one data line and any data in said last line to generate an error checking vector, and iterate the error checking calculation on said appended error checking code using said error checking vector to provide a calculated error checking result; c) a vector selector configured to insert a pad vector to said first data line when said partitioned transmitted data and appended error checking code comprises a remainder, said remainder having any length less than said first fixed length and greater than zero, and select one of a plurality of error checking vectors, said plurality of error checking vectors comprising an initial vector and an error checking code feedback vector, the pad vector having a length providing said first data line with said first fixed length when appended to said remainder; and d) a logic circuit configured to determine a state of said calculated error checking result and, if said calculated error checking result has a predetermined state, indicate that there is no error in said transmitted data. 23. The circuit of claim 22, wherein said pad vector comprises a zero-pad vector. 24. The circuit of claim 22, wherein said set of pad vectors comprises a plurality of zero-pad vectors, each having a unique length. 25. The circuit of claim 22, wherein said first fixed length is 2m bits, where m is an integer of from 6 to 10. 26. The circuit of claim 22, wherein said transmitted data comprises a packet or frame. 27. The circuit of claim 22, wherein said error checking code calculation circuit comprises a cyclic redundancy checking (CRC) circuit. 28. The circuit of claim 22, wherein said predetermined state comprises a block of digital bits, where each bit in the block has the same digital value. 29. The circuit of claim 22, wherein said logic circuit further comprises a demultiplexer configured to output transmitted data error checking code calculated on said transmitted data or said state of said calculated error checking code, depending on a control signal state. 30. The circuit of claim 22, further comprising a storage circuit configured to store said set of pad vectors. 31. The circuit of claim 30, wherein said storage circuit comprises a hash table or a look-up table. 32. The circuit of claim 22, further comprising a remainder logic circuit configured to generate a remainder information signal having a state corresponding to a length of said remainder. 33. The circuit of claim 32, wherein said vector selector selects said one of said pad vectors in response to said remainder information signal. 34. A receiver, comprising: a) the circuit of claim 22; b) a processor in communication with said circuit, configured to process said transmitted data; and c) a clock recovery circuit configured to recover a clock signal from serial transmitted data received by said receiver. 35. The receiver of claim 34, embodied on a single integrated circuit. 36. The receiver of claim 34, wherein said data partitioning circuit comprises a deserializer configured to convert serial digital data into parallel digital data for processing by said error checking code calculation circuit. 37. The receiver of claim 34, wherein said transmitted data comprises a packet or frame. 38. The receiver of claim 37, wherein said processor is further configured to assemble (i) non-data information from said packet or frame and (ii) at least part of said transmitted data. 39. The receiver of claim 38, further comprising a decoder configured to decode at least part of said non-data information. 40. A system for transferring data on or across a network, comprising: a) the receiver of claim 34; b) at least one transmitter in communication with said receiver, said transmitter being configured to transmit said transmitted data to said receiver; and c) at least one receiver port in communication with said receiver for receiving said transmitted data. 41. The system of claim 40, further comprising a control bus configured to transmit an indicator signal from said receiver to said transmitter, said indicator signal indicating whether there is an error in said transmitted data. 42. The system of claim 40, wherein said error checking code calculation circuit comprises a cyclic redundancy checking (CRC) circuit. 43. The system of claim 42, wherein said transmitter further comprises (i) a CRC generator configured to generate CRC information from said transmitted data and (ii) a transmitter processor configured to append said CRC information to said transmitted data. 44. A network, comprising: a) a plurality of the systems of claim 40, in communication with each other; and b) a plurality of storage or communications devices, each of said storage or communications devices being in communication with one of said systems. 45. The network of claim 44, wherein said plurality of storage or communications devices comprises a plurality of storage devices. 46. A circuit for determining a data transmission error and/or confirming an error determination, comprising: a) means for receiving and then partitioning said transmitted data and said appended error checking code into (i) at least one data line having a first fixed length, and (ii) a last line comprising said appended error checking code and having said first fixed length; b) means for performing error checking calculations on a first data line, said at least one data line and any data in said last line to generate an error checking vector, and iterating the error checking calculation on said appended error checking code using said error checking vector to provide a calculated error checking result; c) means for selecting one of a plurality of error checking vectors, said plurality of error checking vectors comprising an initial vector, an error checking code feedback vector, and a pad vector; d) means of inserting said pad vector to said first data line when said partitioned transmitted data and said appended error checking code comprises a remainder, said remainder having any length less than said first fixed length and greater than zero, said pad vector having a length providing said first data line with said first fixed length when appended to said remainder; and e) means for determining a state of said calculated error checking result and, if said calculated error checking result has a predetermined state, indicating that there is no error in said transmitted data. 47. The circuit of claim 46, wherein said pad vector comprises a zero-pad vector. 48. The circuit of claim 46, wherein said set of pad vectors comprises a plurality of zero-pad vectors, each having a unique length. 49. The circuit of claim 46, further comprising a means for storing said set of pad vectors. 50. The circuit of claim 46, wherein said fixed length is 2m bits, where m is an integer of from 6 to 10. 51. The circuit of claim 46, wherein said transmitted data comprises a packet or frame. 52. The circuit of claim 46, wherein said means for calculating error checking code comprises a cyclic redundancy checking (CRC) circuit. 53. The circuit of claim 46, wherein said predetermined state comprises a block of digital bits, where each bit in the block has the same digital value. 54. The circuit of claim 46, wherein said means for determining and indicating further comprises a means for outputting (i) error checking code calculated on said transmitted data by said means for calculating or (ii) said state of said calculated error checking code. 55. The circuit of claim 46, further comprising a means for generating a remainder information signal having a state corresponding to a length of said remainder. 56. The circuit of claim 55, wherein said means for selecting selects said one of said pad vectors in response to said remainder information signal. 57. A receiver, comprising: a) the circuit of claim 46; b) a means for processing in communication with said circuit, configured to process said transmitted data; and c) a means for recovering a clock signal from serial data received by said receiver. 58. The receiver of claim 57, embodied on a single integrated circuit. 59. The receiver of claim 57, further comprising a means for dividing said recovered clock. 60. The receiver of claim 57, wherein said means for calculating error checking code comprises a means for calculating cyclic redundancy code. 61. The receiver of claim 57, wherein said transmitted data comprises a packet or frame. 62. The receiver of claim 61, wherein said means for processing comprises a means for assembling (i) non-data information from said packet or frame and (ii) said transmitted data. 63. The receiver of claim 62, further comprising a means for decoding at least part of said non-data information. 64. A system for transferring data on or across a network, comprising: a) the receiver of claim 57; b) a means for transmitting said transmitted data and said appended error checking code to said receiver; and c) at least one means for receiving said transmitted data and said appended error checking code, said means for receiving being in communication with said receiver. 65. The system of claim 64, wherein said means for transmitting further comprises (i) a second means for calculating error checking code on said transmitted data and (ii) a means for appending said error checking code to said transmitted data. 66. The system of claim 64, wherein said receiver further comprises a means for generating an indicator signal in response to at least one of (i) an error in said transmitted data and/or said appended error checking code and (ii) no error in said transmitted data and/or said appended error checking code detected by said means for calculating. 67. A network, comprising: a) a plurality of the systems of claim 64, in communication with each other; and b) a plurality of means for storing or means for communicating data, each of said means for storing or means for communicating data being in communication with at least one of said systems. 68. The network of claim 67, wherein said plurality of means for storing or means for communicating data comprises a plurality of means for storing.

이 특허에 인용된 특허 (46)

이 특허를 인용한 특허 (13)

IPC 상위 출원인

내보내기

상세정보
내보내기 구분	파일저장 인쇄 메일전송
구성항목	관리번호, 국가코드, 자료구분, 상태, 출원번호, 출원일자, 공개번호, 공개일자, 등록번호, 등록일자, 발명명칭(한글), 발명명칭(영문), 출원인(한글), 출원인(영문), 출원인코드, 대표IPC 관리번호, 국가코드, 자료구분, 상태, 출원번호, 출원일자, 공개번호, 공개일자, 공고번호, 공고일자, 등록번호, 등록일자, 발명명칭(한글), 발명명칭(영문), 출원인(한글), 출원인(영문), 출원인코드, 대표출원인, 출원인국적, 출원인주소, 발명자, 발명자E, 발명자코드, 발명자주소, 발명자 우편번호, 발명자국적, 대표IPC, IPC코드, 요약, 미국특허분류, 대리인주소, 대리인코드, 대리인(한글), 대리인(영문), 국제공개일자, 국제공개번호, 국제출원일자, 국제출원번호, 우선권, 우선권주장일, 우선권국가, 우선권출원번호, 원출원일자, 원출원번호, 지정국, Citing Patents, Cited Patents
저장형식	Text(ASCII format) Excel format PIAS분석(.xls)
메일정보	받는사람 (필수) @ 보내는사람 (선택) @ 제목 내용 KISTI 검색결과 이메일 서비스
안내	> 총 건의 자료가 검색되었습니다. > 다운받으실 자료의 인덱스를 입력하세요. (1-10,000) > 검색결과의 순서대로 최대 10,000건 까지 다운로드가 가능합니다. > 데이타가 많을 경우 속도가 느려질 수 있습니다.(최대 2~3분 소요) > 다운로드 파일은 UTF-8 형태로 저장됩니다. 파일의 내용이 제대로 보이지 않을실 때는 웹브라우저 상단의 보기 -> 인코딩 -> 자동선택 여부를 확인하십시오 > ~ > Text(ASCII format) Excel format

과학기술 지식인프라 ScienceON

ScienceON Chatbot

연합인증

특허 상세정보

Methods, circuits, architectures, software and systems for determining a data transmission error and/or checking or confirming such error determinations

초록
▼

대표
청구항
▼

이 특허에 인용된 특허 (46)

이 특허를 인용한 특허 (13)

IPC 상위 출원인

과제정보

상세정보조회

원문조회

IPC 상세정보(version : 201201)

연구과제 성과물(0)

참여연구원의 다른 문헌(0)

처리중입니다.

잠시만 기다려주세요.

ScienceON Chatbot

연합인증

특허 상세정보

Methods, circuits, architectures, software and systems for determining a data transmission error and/or checking or confirming such error determinations

초록 ▼

대표청구항 ▼

이 특허에 인용된 특허 (46)

이 특허를 인용한 특허 (13)

IPC 상위 출원인

과제정보

상세정보조회

원문조회

IPC 상세정보(version : 201201)

연구과제 성과물(0)

참여연구원의 다른 문헌(0)

처리중입니다.

잠시만 기다려주세요.

초록
▼

대표
청구항
▼