초록 ▼

A method of fabricating a semiconductor device having a capacitor is provided. The method includes forming second, third, fourth, and fifth insulating layers on a first conductive layer formed in a first insulating layer. The fourth insulating layer is patterned into a first pattern before forming t

A method of fabricating a semiconductor device having a capacitor is provided. The method includes forming second, third, fourth, and fifth insulating layers on a first conductive layer formed in a first insulating layer. The fourth insulating layer is patterned into a first pattern before forming the fifth insulating layer thereupon. A capacitor and contact plug are formed by etching the fifth insulating layer to expose the first pattern; etching the third insulating layer using the exposed first pattern as a mask to expose the second insulating layer; exposing the first conductive layer at a capacitor region and contact plug region by etching the exposed second insulating layer; forming a second conductive layer on the exposed first conductive layer and sidewalls of the insulating layers; forming a dielectric on the second conductive layer in the capacitor region; and filling the capacitor and contact plug regions with a third conductive layer.

대표청구항 ▼

I claim: 1. A method for manufacturing a semiconductor device, the method comprising the steps of: forming a first insulating layer on a top surface of a semiconductor substrate; etching the first insulating layer to form a trench; depositing a first conductive layer on the insulating layer and fil

I claim: 1. A method for manufacturing a semiconductor device, the method comprising the steps of: forming a first insulating layer on a top surface of a semiconductor substrate; etching the first insulating layer to form a trench; depositing a first conductive layer on the insulating layer and filling the trench; performing a first planarization process to expose a top surface of the first insulating layer while leaving the first conductive layer in the trench; sequentially forming a second insulating layer, a third insulating layer, and a fourth insulating layer on the planarized first insulating layer; etching the fourth insulating layer to form a first pattern for a contact plug area and a capacitor area of the first conductive layer; depositing a fifth insulating layer on the fourth insulating layer having the first pattern and planarizing the fifth insulating layer; forming a second pattern on the fifth insulating layer to expose the fifth insulating layer on the contact plug area and the capacitor area; etching the exposed fifth insulating layer using the second pattern as a mask to expose the first pattern; etching the third insulating layer using the first pattern as a mask to expose the second insulating layer; etching the exposed second insulating layer to expose the first conductive layer in the contact plug area and the capacitor area; forming a second conductive layer on the exposed first conductive layer and inner sidewalls of the exposed second, third, fourth, and fifth insulating layers; forming a capacitor insulating layer on the second conductor formed in the capacitor area; and forming a third conductive layer in the contact plug area and the capacitor area. 2. The method according to claim 1, wherein the second conductive layer corresponds to a capacitor bottom electrode, and the third conductive layer formed in the capacitor area corresponds to a capacitor top electrode. 3. The method according to claim 1, wherein the second conductive layer comprises tantalum nitride (TaN) or a multi-layer including tantalum nitride (TaN). 4. The method according to claim 1, wherein the second conductive layer comprises titanium nitride (TiN) or a multi-layer including titanium nitride (TiN). 5. The method according to claim 1, wherein the second conductive layer comprises tungsten nitride (WN) or a multi-layer including tungsten nitride (WN). 6. The method according to claim 1, wherein the capacitor insulating layer comprises a nitride layer, TEOS (Tetraethoxysilane), tantalum based oxide, or aluminum based oxide. 7. The method according to claim 1, wherein the second insulating layer and the fourth insulating layer are formed of the same material. 8. The method according to claim 1, wherein the second insulating layer and the fourth insulating layer are formed of a nitride layer, SiC (silicon carbide), or aluminum oxide. 9. The method according to claim 7, wherein the fourth insulating layer has a thickness larger than a thickness of the second insulating layer. 10. The method according to claim 1, wherein etching the third insulating layer using the first pattern as a mask and etching the exposed second insulating layer forms a meander structure in the second and third insulating layers on the capacitor area of first conductive layer. 11. The method according to claim 1, wherein etching the third insulating layer using the first pattern as a mask and etching the exposed second insulating layer forms a spiral structure in the second and third insulating layers on the capacitor area of the first conductive layer.