초록 ▼

Provided is a DC-DC converter including a short-circuit protection circuit which can stably perform a reset operation and a stop operation. The short-circuit protection circuit includes a detection circuit, a delay circuit, and a latch circuit. The delay circuit is reset in response to an output vol

Provided is a DC-DC converter including a short-circuit protection circuit which can stably perform a reset operation and a stop operation. The short-circuit protection circuit includes a detection circuit, a delay circuit, and a latch circuit. The delay circuit is reset in response to an output voltage abnormality signal related to a switching regulator which is outputted from the latch circuit. The latch circuit is reset based on an AND operation between the output voltage abnormality signal and a UVLO signal.

대표청구항 ▼

What is claimed is: 1. A DC-DC converter, comprising a timer latch short-circuit protection circuit, including: a detection circuit for detecting a voltage of an output terminal and generating an output abnormality detection signal when the voltage of the output terminal reduces; a delay circuit fo

What is claimed is: 1. A DC-DC converter, comprising a timer latch short-circuit protection circuit, including: a detection circuit for detecting a voltage of an output terminal and generating an output abnormality detection signal when the voltage of the output terminal reduces; a delay circuit for generating an output abnormality signal when the output abnormality detection signal is inputted thereto for at least a predetermined time; and a latch circuit for holding the output abnormality signal, wherein the delay circuit is reset in response to the output abnormality signal outputted from the latch circuit. 2. A DC-DC converter according to claim 1, wherein: the DC-DC converter further comprises a UVLO circuit for generating a UVLO signal when a reduction in input power source voltage is detected; and the latch circuit is reset based on an AND operation between the output abnormality signal and the UVLO signal. 3. A DC-DC converter according to claim 1, wherein the delay circuit includes: a constant current circuit and a capacitor which are connected in series between a power source terminal and a ground terminal; a switching element which is connected in parallel with the capacitor and controlled based on the output abnormality detection signal; and a comparator circuit for monitoring a voltage of the capacitor and generating the output abnormality signal when the monitored voltage reaches a predetermined voltage. 4. A DC-DC converter according to claim 3, wherein the switching element is controlled based on the output abnormality detection signal from the detection circuit to charge the capacitor and controlled based on the output abnormality signal from the latch circuit to discharge the capacitor. 5. A DC-DC converter, comprising: an inductance and a diode which are connected in series between an input power source terminal and an output voltage terminal; a voltage dividing circuit for generating a divided voltage of an output voltage of the output voltage terminal; a reference voltage circuit for generating a reference voltage; an error amplifier circuit for generating a voltage corresponding to a result obtained by comparison between the divided voltage from the voltage dividing circuit and the reference voltage; an oscillator circuit for generating a triangular wave; a PWM comparator for comparing the voltage generated from the error amplifier circuit with the triangular wave and generating a rectangular wave; a switching element connected between a connection portion between the inductance and the diode and a ground terminal; a detection circuit for detecting a presence or absence of abnormality of the voltage generated from the error amplifier circuit; a delay circuit for delaying an output signal from the detection circuit by a predetermined time; and a latch circuit for latching an output signal from the delay circuit, wherein the delay circuit is reset in response to the output signal from the latch circuit. 6. A DC-DC converter according to claim 5, further comprising a UVLO circuit, wherein the latch circuit is reset based on an AND operation between a UVLO signal outputted from the UVLO circuit when a reduction in input power source voltage is detected and the output signal from the latch circuit. 7. A DC-DC converter according to claim 5, wherein the delay circuit includes: a constant current circuit and a capacitor which are connected in series between the input power source terminal and a ground terminal; a switching element which is connected in parallel with the capacitor and controlled based on an output abnormality detection signal generated by the detection circuit when the presence of an abnormality of the voltage generated from the error amplifier circuit is detected; and a comparator circuit for monitoring a voltage of the capacitor and generating the output abnormality signal when the monitored voltage reaches a predetermined voltage.