$\require{mediawiki-texvc}$

연합인증

연합인증 가입 기관의 연구자들은 소속기관의 인증정보(ID와 암호)를 이용해 다른 대학, 연구기관, 서비스 공급자의 다양한 온라인 자원과 연구 데이터를 이용할 수 있습니다.

이는 여행자가 자국에서 발행 받은 여권으로 세계 각국을 자유롭게 여행할 수 있는 것과 같습니다.

연합인증으로 이용이 가능한 서비스는 NTIS, DataON, Edison, Kafe, Webinar 등이 있습니다.

한번의 인증절차만으로 연합인증 가입 서비스에 추가 로그인 없이 이용이 가능합니다.

다만, 연합인증을 위해서는 최초 1회만 인증 절차가 필요합니다. (회원이 아닐 경우 회원 가입이 필요합니다.)

연합인증 절차는 다음과 같습니다.

최초이용시에는
ScienceON에 로그인 → 연합인증 서비스 접속 → 로그인 (본인 확인 또는 회원가입) → 서비스 이용

그 이후에는
ScienceON 로그인 → 연합인증 서비스 접속 → 서비스 이용

연합인증을 활용하시면 KISTI가 제공하는 다양한 서비스를 편리하게 이용하실 수 있습니다.

Pad structures to improve board-level reliability of solder-on-pad BGA structures 원문보기

IPC분류정보
국가/구분 United States(US) Patent 등록
국제특허분류(IPC7판)
  • H01L-023/48
  • H01L-023/02
  • H01L-021/00
출원번호 US-0911088 (2004-08-04)
등록번호 US-7446399 (2008-11-04)
발명자 / 주소
  • Li,Yuan
출원인 / 주소
  • Altera Corporation
대리인 / 주소
    Morgan, Lewis & Bockius LLP
인용정보 피인용 횟수 : 2  인용 특허 : 34

초록

The present invention is directed to a new bonding pad structure having a rugged contact interface that makes it more difficult for a crack to grow from the peripheral edge of the bonding pad. The rugged contact interface also helps to accumulate more solder paste on the edge of the bonding pad, inc

대표청구항

What is claimed is: 1. An electronic package, the package comprising: a substrate having a top side and a bottom side; a semiconductor die attached to a first array of bonding pads on the top side of the substrate; and an array of solder balls attached to a second array of bonding pads on the botto

이 특허에 인용된 특허 (34)

  1. Kimura Naoto (Kumamoto JPX), Ball grid array type of semiconductor device.
  2. Jiang, Tongbi; Akram, Salman, Ball grid array utilizing solder balls having a core material covered by a metal layer.
  3. Huang Yung-Sheng,TWX ; Lin Chiu-Ching,TWX ; Lu Chun-Hung,TWX ; Hwang Ruey-Lian,TWX, Bonding pad structure to prevent inter-metal dielectric cracking and to improve bondability.
  4. Shih Wei-Yan ; Wilson Arthur ; Subido Willmar, Bonding pads for integrated circuits having copper interconnect metallization.
  5. Kleffner James H. ; Mistry Addi Burjorji, Bumped semiconductor device having a trench for stress relief.
  6. Hirano Naohiko (Kawasaki JPX) Doi Kazuhide (Kawasaki JPX) Miura Masayuki (Kawasaki JPX) Okada Takashi (Kawasaki JPX) Hiruta Yoichi (Kashiwa JPX), Connecting electrode portion in semiconductor device.
  7. Casson Keith L. (Northfield MN) Habeck Kelly D. (Tampa FL) Selbitschka Eugene T. (South St. Paul MN), Direct application of unpackaged integrated circuit to flexible printed circuit.
  8. Gerber Joel A. (Saint Paul MN) Gits Peter A. (White Bear Lake MN), Electrical interconnections between adjacent circuit board layers of a multi-layer circuit board.
  9. Galloway Terry R., Extended bond pads with a plurality of perforations.
  10. Lee, Teck Kheng, Innovative solder ball pad structure to ease design rule, methods of fabricating same and substrates, electronic device assemblies and systems employing same.
  11. Sidney Larry Anderson, Integrated circuit package utilizing a conductive structure for interlocking a conductive ball to a ball pad.
  12. Lee, Jong-Myoung, Lead on chip type semiconductor package.
  13. Berndlmaier Erich (Wappingers Falls NY) Das Gobinda (Hopewell Junction NY) Viau Thomas L. (Milton VT), Metal bump for a thermal compression bond and method for making same.
  14. Berndlmaier Erich (Wappingers Falls NY) Das Gobinda (Hopewell Junction NY) Viau Thomas L. (Milton VT), Metal bump for a thermal compression bond and method for making same.
  15. Tellkamp,John P., Metallic strain-absorbing layer for improved fatigue resistance of solder-attached devices.
  16. Haim Feigenbaum ; Chris M. Schreiber, Method for joining an integrated circuit.
  17. Angulas Christopher G. (Endicott) Flynn Patrick T. (Owego) Funari Joseph (Vestal) Kindl Thomas E. (Endwell) Orr Randy L. (Vesal NY), Method of bonding flexible circuit to cicuitized substrate to provide electrical connection therebetween using different.
  18. Bitaillou Alexis (Bretigny sur Orge FRX) Grandguillot Michel (Verrieres le Buisson FRX), Method of forming solder terminals for a pinless ceramic module.
  19. Hsu, Chi-Hsing, Method of making wafer level packaging and chip structure.
  20. Tanaka Yasuyuki (Tsuchiura JPX) Oomachi Chikafumi (Kashiwa JPX), Method of manufacture of multilayer circuit board.
  21. Kondo Hiroshi (Yokohama JPX) Yoshizawa Tetsuo (Yokohama JPX) Miyazaki Toyohide (Ibaraki-ken JPX) Terayama Yoshimi (Odawara JPX) Sakaki Takashi (Tokyo JPX) Ikegami Yuichi (Osaka JPX) Okabayashi Takahi, Method of manufacturing electrical connecting member.
  22. Andrascek Ernst (Munich DEX) Hadersbeck Hans (Munich DEX), Method of producing copper platforms for integrated circuits.
  23. Wu Zhiqiang ; Jiang Tongbi ; Akram Salman, Methods for forming conductive micro-bumps and recessed contacts for flip-chip technology and method of flip-chip assembly.
  24. Tanaka Yasuyuki (Tsuchiura JPX) Oomachi Chikafumi (Kashiwa JPX), Multilayer circuit board for mounting ICs and method of manufacturing the same.
  25. Fitzsimmons,John A.; Gambino,Jeffrey P.; Walton,Erick G., Roughened bonding pad and bonding wire surfaces for low pressure wire bonding.
  26. Kobayashi Syoichi,JPX ; Koizumi Naoyuki,JPX ; Uehara Osamu,JPX ; Iizuka Hajime,JPX, Semiconductor device and process for producing same.
  27. Matsuda Shuichi,JPX ; Shoji Kazutaka,JPX, Semiconductor device with increased multi-bumps and adhered multilayered insulating films and method for installing same.
  28. Larson Charles ; Fernandez John, Semiconductor lead frame and package with stiffened mounting paddle.
  29. Soga, Tasao; Hata, Hanae; Nakatsuka, Tetsuya; Negishi, Mikio; Nakajima, Hirokazu; Endoh, Tsuneo, Solder.
  30. Lee Moo Eung,KRX, Solder ball land metal structure of ball grid semiconductor package.
  31. Weiss Michael L. (Coral Springs FL), Surface mount interposer.
  32. Workman,Derek B.; Chaundhuri,Arun K.; Berg,Eric M, Underfill method.
  33. Chao Ying-Chen,TWX ; Lin Ting-Hwang,TWX ; Lee Jin-Yuan,TWX, Upward plug filled via hole device.
  34. William J. Clatanoff ; Gayle R. T. Schueller ; Robert J. Schubert ; Yusuke Saito JP; Hideo Yamazaki JP; Hideaki Yasui JP, Via plug adapter.

이 특허를 인용한 특허 (2)

  1. Yang, Chih-Kuang, Metal structure of flexible multi-layer substrate and manufacturing method thereof.
  2. Hutchinson, Erik Jon; Unger, Christopher Michael, Slider bond pad with a recessed channel.
섹션별 컨텐츠 바로가기

AI-Helper ※ AI-Helper는 오픈소스 모델을 사용합니다.

AI-Helper 아이콘
AI-Helper
안녕하세요, AI-Helper입니다. 좌측 "선택된 텍스트"에서 텍스트를 선택하여 요약, 번역, 용어설명을 실행하세요.
※ AI-Helper는 부적절한 답변을 할 수 있습니다.

선택된 텍스트

맨위로