초록 ▼

A neural network component includes a plurality of inputs, at least one processing element, at least one output, and a digital memory storing values at addresses respectively corresponding to the at least one processing element, wherein the at least one processing element is arranged to receive a va

A neural network component includes a plurality of inputs, at least one processing element, at least one output, and a digital memory storing values at addresses respectively corresponding to the at least one processing element, wherein the at least one processing element is arranged to receive a value from the digital memory in response to an input signal, and is instructed to execute one of a plurality of operations by the value that is received from the digital memory.

대표청구항 ▼

What is claimed is: 1. A neural network component, the component comprising: an addressable digital memory; a plurality of inputs configured to receive addresses for locations in said digital memory; at least one processing element for performing a plurality of different operations based on respect

What is claimed is: 1. A neural network component, the component comprising: an addressable digital memory; a plurality of inputs configured to receive addresses for locations in said digital memory; at least one processing element for performing a plurality of different operations based on respectively corresponding values received from memory locations addressed via said inputs; at least one output providing the result of processing performed by said processing element; and said digital memory storing values representing processing element instructions at addresses respectively corresponding to the processing elements, said instructions corresponding to different operations; wherein the at least one processing element is configured to receive one of said stored values from the digital memory in response to a signal at an input, and is thereby instructed to execute a corresponding one of said plurality of operations by the value that is received from the digital memory; and wherein one of said plurality of different operations comprises generation of an output by the at least one processing element, and then resetting an activation level of the at least one processing element to a predetermined minimum level. 2. A neural network component, the component comprising: an addressable digital memory; a plurality of inputs configured to receive addresses for locations in said digital memory; at least one processing element for performing a plurality of different operations based on respectively corresponding values received from memory locations addressed via said inputs; at least one output providing the result of data processing performed by said processing element; and said digital memory storing values representing processing element instructions at addresses respectively corresponding to the processing elements, said instructions corresponding to different operations; wherein the at least one processing element is configured to receive one of said stored values from the digital memory in response to a signal at an input, and is thereby instructed to execute a corresponding one of said plurality of operations by the value that is received from the digital memory; and wherein one of said plurality of different operations comprises resetting an activation level of the at least one processing element to a predetermined minimum level without an output being generated by the at least one processing element. 3. A method of operating a neural network component, the method comprising: storing values representing neural network processing element instructions in a digital memory at addresses respectively corresponding to neural network processing elements; transferring one of said stored values representing an instruction to at least one said processing element; and executing one of a plurality of pre-determined different operations at the processing element in response to the respectively corresponding value that is received from the digital memory; wherein said plurality of pre-determined operations include at least one of: (a) changing an activation level of a neuron processing element by (i) increasing the neuron activation level if the value is negative or (ii) decreasing the neuron activation level if the value is positive; (b) decaying a neuron activation level dependent upon the instruction value; (c) generating a neuron output and then resetting the activation level of the neuron to a predetermined minimum level; (d) resetting a neuron activation level to a predetermined minimum level without generating an output; (e) modifying a neuron activation level in accordance with an automatic learning algorithm; and (f) modifying the value held in memory for a neuron in accordance with an automatic learning algorithm. 4. A method for providing a neural network component having neuron activity levels that are controllable to be either monotonic or non-monotonic functions of neuron inputs, said method comprising: receiving a neuron processing instruction from a respectively associated digital memory location addressed by a neuron input signal; if the received instruction falls within a first predetermined range, performing a neuron processing function which monotonically changes the neuron's activity level; and if the received instruction falls within a second predetermined range, performing a neuron processing function which non-monotonically changes the neuron's activity level. 5. A neural network component having neuron activity levels that are controllable to be either monotonic or non-monotonic functions of neuron inputs, said component comprising: means for receiving a neuron processing instruction from a respectively associated digital memory location addressed by a neuron input signal; means for determining if the received instruction falls within a first predetermined range, and, if so, performing a neuron processing function which monotonically changes the neuron's activity level; and means for determining if the received instruction falls within a second predetermined range, and, if so, performing a neuron processing function which non-monotonically changes the neuron's activity level. 6. A method of providing a neural network component having a neuron activity level that can be a non-monotonic function of its inputs, said method comprising: storing processing instructions for each of plural processing elements in respective locations of a read-write digital memory addressed by inputs to said processing elements; receiving a processing instruction from said memory for a processing element in response to a received input; if the received processing instruction falls within a first predetermined range, adding the received instruction to the respectively corresponding neuron activation level thus causing a monotonic change in its activation level; if the received processing instruction falls into a second predetermined range, adding the received instruction to the respectively corresponding neuron activation level and storing a different processing instruction in said memory for subsequent use by the respectively corresponding neuron; and if the received processing instruction falls into a third predetermined range, performing an operation for the respectively corresponding neuron that is based on the received instruction and including at least one of the following operations: (a) decay of an activation level to zero, by increasing the activation level if it is negative or decreasing the activation level if it is positive; (b) generation of an output and then resetting an activation level to a predetermined minimum level; (c) resetting an activation level to a predetermined minimum level without an output being generated; (d) modifying an activation level in accordance with an automatic learning algorithm; and (e) modifying the corresponding processing instruction value held in the digital memory in accordance with an automatic learning algorithm. 7. A method as in claim 6 wherein said decay is at a rate dependent upon the received instruction. 8. A method as in claim 6 wherein said decay is at a rate controlled by a clock. 9. A method as in claim 6 wherein said automatic learning algorithm comprises a Hebbian learning algorithm. 10. A method as in claim 6, wherein an output generated from a neural network component represents the digital memory address associated with the neural processing element from which the output emanated. 11. A method as in claim 6 further comprising: determining the chronological order of signal pulses received from neural processing elements; and representing each signal pulse as a multi-digit digital value corresponding to the digital memory address associated with the neural processing element from which the output emanated. 12. A method as in claim 6 further comprising: asynchronously arbitrating accesses to at least one computer processor for performing processes associated with plural neural processing elements.