초록 ▼

Provided is a parallel data path architecture for high energy efficiency. In this architecture, a plurality of parallel process units and a plurality of function units of the process units are controlled by instructions and processed in parallel to improve performance. Also, since only necessary pro

Provided is a parallel data path architecture for high energy efficiency. In this architecture, a plurality of parallel process units and a plurality of function units of the process units are controlled by instructions and processed in parallel to improve performance. Also, since only necessary process units and function units are enabled, power dissipation is reduced to enhance energy efficiency. Further, by use of a simple instruction format, hardware can be programmed as the parallel data path architecture for high energy efficiency, which satisfies both excellent performance and low power dissipation, thus elevating hardware flexibility.

대표청구항 ▼

What is claimed is: 1. A parallel data path architecture, comprising: a processing unit array including a plurality of processing units, each of the processing units comprising: a data bus; an instruction register operable for receiving a reset signal, synchronizing an instruction transmitted throu

What is claimed is: 1. A parallel data path architecture, comprising: a processing unit array including a plurality of processing units, each of the processing units comprising: a data bus; an instruction register operable for receiving a reset signal, synchronizing an instruction transmitted through an instruction bus with a first clock signal, and storing the instruction; an instruction decoder operable for receiving the first clock signal and a second clock signal, decoding the instruction stored by the instruction register, and producing a first control signal, a second control signal, and a third control signal corresponding to the instruction; register files operable for receiving the reset signal and the first control signal, wherein a register file among said register files is selected and controlled corresponding to the decoded instruction in response to the first control signal; a load/store unit operable for receiving the first and second clock signals, controlling data transmission to and from an external memory connectable to the data bus in response to the second control signal, and transmitting and receiving data to and from the register files; and first through third operation logic units that are selectively enabled in response to the third control signal and operable for executing the instruction and outputting results to the register files; wherein said instruction decoder is further operable for: outputting processing unit selection (PUSel) signals and register file selection (RFSel) signals, receiving one of said PUSel signals, via a first feedback line, as a processing unit selection input (PUIN) signal that selectively selects the processing unit to handle the instruction, and receiving one of said RFSel signals, via a second feedback line, as a register file selection input (RFIN) signal that selectively selects at least one of the register files of said processing unit for access by the external memory; wherein only the selected processing unit(s) and its/their selected register file(s) are enabled according to the instruction, thereby reducing power consumption and enhancing energy efficiency of the parallel data path architecture. 2. The parallel data path architecture according to claim 1, wherein the RFIN and RFSel signals of the instruction decoder of each of the processing units are controlled by the instruction bus. 3. The parallel data path architecture according to claim 1, wherein the PUIN and PUSel signals of the instruction decoder of each of the processing units are controlled by the instruction bus. 4. The parallel data path architecture according to claim 1, wherein each of the processing units includes a data path that is connected in parallel to the instruction bus and connected to the external memory through the respective data bus. 5. The parallel data path architecture according to claim 1, wherein each of the processing units further includes: a RFSel terminal and a PUSel terminal at which the RFSel and PUSel signals are outputted, respectively; and a RFIN terminal and a PUIN terminal at which the RFIN and PUIN signals are received, respectively; wherein the RFSel terminal and the PUSel terminal are directly electrically connected to the RFIN terminal and the PUIN terminal via the second and first feedback lines, respectively. 6. The parallel data path architecture according to claim 1, wherein said away comprises multiple rows and columns each comprising multiple said processing units; and all said processing units share the same instruction bus, but have respectively different data buses all connectable to the external memory. 7. The parallel data path architecture according to claim 6, being a Single Instruction, Multiple Data (SIMD) architecture.