[특허]Method of forming high aspect ratio structures

[미국특허] Method of forming high aspect ratio structures 원문보기

IPC분류정보
국가/구분	United States(US) Patent 등록
국제특허분류(IPC7판)	H01L-021/302 H01L-021/02
출원번호	US-0788899 (2004-02-27)
등록번호	US-7468323 (2008-12-23)
발명자 / 주소	Torek,Kevin Shea,Kevin Graettinger,Thomas
출원인 / 주소	Micron Technology, Inc.
대리인 / 주소	Schwegman, Lundberg & Woessner, P.A.
인용정보	피인용 횟수 : 3 인용 특허 : 40

초록 ▼

An etching process includes providing a dielectric first film on a substrate and a sacrificial second film on the dielectric first film. A conductive structure such as a container capacitor is formed in a recess in the first and second films. The conductive structure is exposed as to its external su

대표청구항 ▼

The invention claimed is: 1. A process comprising: forming a first dielectric layer on a substrate; forming a second dielectric layer on the first dielectric layer; forming a first recess having a first lateral dimension at a bottom portion of the first dielectric layer in contact with the substrate, and having a second lateral dimension at a top portion of the second dielectric layer; forming a conductive structure in the first recess having vertical sidewalls with the first lateral dimension having a value approximately equal to a value of the second lateral dimension; first wet etching to expose a first portion of the conductive structure by removing at least a portion of the second dielectric layer; first rinsing the conductive structure; and second non-wet etching to expose a second portion of the conductive structure by removing at least a remaining portion of the first dielectric layer and exposing at least a portion of the substrate. 2. The process of claim 1, wherein the second dielectric film includes a polysilicon film. 3. The process of claim 1, wherein first wet etching has a rate that is faster than second non-wet etching. 4. The process of claim 1, wherein the first wet etching is selected from the group consisting of a wet process and a vapor process, and wherein the second non-wet etching is selected from the group consisting of a vapor process and a dry process. 5. The process of claim 1, wherein the substrate includes a single dielectric stack, wherein first wet etching is selected from the group consisting of a wet process and a vapor process, wherein second non-wet etching is selected from the group consisting of a vapor process and a dry process, and wherein the single dielectric stack is selected from the group consisting of undoped spin-on dielectric, undoped vapor-deposited dielectric, doped spin-on dielectric, and doped vapor-deposited dielectric. 6. The process of claim 1, wherein the substrate includes a single dielectric stack, wherein first wet etching is selected from the group consisting of a wet process and a vapor process, wherein second non-wet etching is selected from the group consisting of a vapor process and a dry process, and wherein the single dielectric stack is selected from the group consisting of spin-on undoped silica, spin-on doped silica, borophospho silicate glass, borosilicate glass, phospho silicate glass, doped oxide from the decomposition of tetraethyl ortho silicate, and undoped oxide from the decomposition of tetraethyl ortho silicate. 7. The process of claim 2, wherein forming a first recess includes forming the recess in a dielectric first film that is disposed above the substrate, and in a second film that is disposed above and on the dielectric first film. 8. The process of claim 1, wherein first wet etching includes a first etch chemistry, wherein second non-wet etching includes a second etch chemistry different from the first etch chemistry. 9. The process of claim 1, wherein the first wet etching exposes a first portion of the conductive structure by removing all of the second dielectric layer. 10. The process of claim 1, wherein the first wet etching exposes a first portion of the conductive structure by removing all of the second dielectric layer and exposing at least a portion of the substrate. 11. The process of claim 1, wherein the second dielectric layer further includes a polysilicon layer selected from the group consisting of undoped polysilicon, and heavily doped polysilicon. 12. The process of claim 1, wherein the conductive structure is coupled to a substrate active area. 13. The process of claim 1, wherein the conductive structure includes a container capacitor. 14. The process of claim 1, further including forming a storage cell plate over the conductive structure. 15. The process of claim 1, wherein the conductive structure is formed to extend above a remaining portion of the first dielectric stack to form an exposed vertical portion not in contact with dielectric.

이 특허에 인용된 특허 (40) 인용/피인용 타임라인 분석

Kevin J. Torek ; Donald L. Yates, Acid blend for removing etch residue.
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Torek, Kevin J.; Yates, Donald L., Acid blend for removing etch residue.
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Torek, Kevin J.; Yates, Donald L., Acid blend for removing etch residue.
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Grant Robert W. (Allenstown PA) Ruzyllo Jerzy (State College PA) Torek Kevin (State College PA), Controlled etching of oxides via gas phase reactions.
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Torek, Kevin J.; Morgan, Jonathan C.; Morgan, Paul A., Delivery of dissolved ozone.
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Lee Whonchee ; Torek Kevin J., High selectivity BPSG to TEOS etchant.
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O'Brien Sean C., Hydrofluoric etch quenching via a colder rinse process.
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Morgan Paul A. ; Torek Kevin, Method and apparatus for etch of a specific subarea of a semiconductor work object.
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Wada, Yukihisa, Method for fabricating semiconductor device.
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Gonzalez Fernando (Boise ID) Lee Roger R. (Boise ID), Method for fabricating storage node capacitor having tungsten and etched tin storage node capacitor plate.
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Lin Yeh-Sen,TWX ; Koh Chao-Ming,TWX, Method for manufacturing a capacitor using non-conformal dielectric.
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Chan, Darin; Bonser, Douglas J.; Plat, Marina V.; Wright, Marilyn I.; Yang, Chih Yuh; You, Lu; Bell, Scott A.; Fisher, Philip A., Method for reducing gate line deformation and reducing gate line widths in semiconductor devices.
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Torek Kevin James ; Lee Whonchee ; Bedge Satish, Method for selective etching of anitreflective coatings.
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Torek Kevin James ; Lee Whonchee ; Bedge Satish, Method for selective etching of antireflective coatings.
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Torek Kevin James ; Lee Whonchee ; Bedge Satish, Method for selective etching of antireflective coatings.
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Max F. Hineman ; Kevin J. Torek, Method for selective etching of oxides.
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Torek Kevin J., Method of etching thermally grown oxide substantially selectively relative to deposited oxide.
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Torek Kevin J., Method of etching thermally grown oxide substantially selectively relative to deposited oxide.
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Torek, Kevin J., Method of forming an inset in a tungsten silicide layer in a transistor gate stack.
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Torek Kevin J., Method of making an oxide structure having a finely calibrated thickness.
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Kwean, Sung-Un; Hwang, Jae-Seung, Method of manufacturing a capacitor of a semiconductor device.
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Li Li ; Westmoreland Donald L. ; Hawthorne ; deceased Richard C. ; Torek Kevin, Method of wafer cleaning, and system and cleaning solution regarding same.
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Torek Kevin James (Boise ID) Lee Whonchee (Boise ID) Hawthorne ; deceased Richard C. (late of Nampa ID), Methods and etchants for etching oxides of silicon with low selectivity in a vapor phase system.
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Smith, David; Torek, Kevin J.; Morgan, Paul A., Methods of cleaning surfaces of copper-containing materials, and methods of forming openings to copper-containing substrates.
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Torek, Kevin J.; Derderian, Garo J., Methods of removing at least some of a material from a semiconductor substrate.
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Kevin J. Torek, Oxide structure having a finely calibrated thickness.
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Torek, Kevin J.; Hishiro, Yoshiki, Photoresist developer with reduced resist toppling and method of using same.
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Grant Robert W. (Excelsior MN) Torek Kevin (State College PA) Novak Richard E. (Plymouth MN) Ruzyllo Jerzy (State College PA), Process for etching oxide films in a sealed photochemical reactor.
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Rsner Wolfgang (Mnchen DEX), Process for producing storage capacitors for DRAM cells.
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Torek Kevin J. ; Lee Whonchee, Process for selectively etching silicon nitride in the presence of silicon oxide.
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Torek Kevin J. ; Lee Whonchee, Process for selectively etching silicon nitride in the presence of silicon oxide.
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Torek Kevin James ; Lee Whonchee ; Hawthorne Richard C., Selective etching of oxides.
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Kitamura, Hiroyuki, Semiconductor device and method of forming the same.
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Jost Mark E. ; Howard Bradley J., Semiconductor processing for forming capacitors by etching polysilicon and coating layer formed over the polysilicon.
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Torek, Kevin J.; Bedge, Satish, Semiconductor processing methods.
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Torek, Kevin J.; Bedge, Satish, Semiconductor processing methods utilizing low concentrations of reactive etching components.
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Torek, Kevin J.; Bedge, Satish, Semiconductor processing methods utilizing low concentrations of reactive etching components.
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Li Li ; Westmoreland Donald L. ; Hawthorne Richard C. ; Torek Kevin, System for wafer cleaning.
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Hu, Yongjun Jeff; Bedge, Satish; Torek, Kevin, Techniques for improving wordline fabrication of a memory device.
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Nuttall Michael ; Torek Kevin J. ; Chapek David L., Trench isolation method.
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이 특허를 인용한 특허 (3) 인용/피인용 타임라인 분석

Freeman, Eric H., Capacitor structures having improved area efficiency.
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Freeman, Eric H., Memory devices including capacitor structures having improved area efficiency.
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Freeman, Eric H., Memory devices including capacitor structures having improved area efficiency.
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[미국특허] Method of forming high aspect ratio structures 원문보기