IPC분류정보
국가/구분 |
United States(US) Patent
등록
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국제특허분류(IPC7판) |
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출원번호 |
US-0019783
(2004-12-21)
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등록번호 |
US-7472155
(2008-12-30)
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발명자
/ 주소 |
- Simkins,James M.
- Young,Steven P.
- Wong,Jennifer
- New,Bernard J.
- Ching,Alvin Y.
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출원인 / 주소 |
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대리인 / 주소 |
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인용정보 |
피인용 횟수 :
98 인용 특허 :
85 |
초록
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Described is a programmable logic device (PLD) with columns of DSP slices that can be cascaded to create DSP circuits of varying size and complexity. Each DSP slice includes a plurality of operand input ports and a slice output port, all of which are programmably connected to general routing and log
Described is a programmable logic device (PLD) with columns of DSP slices that can be cascaded to create DSP circuits of varying size and complexity. Each DSP slice includes a plurality of operand input ports and a slice output port, all of which are programmably connected to general routing and logic resources. The operand ports receive operands for processing, and a slice output port conveys processed results. Each slice additionally includes a feedback port connected to the respective slice output port, to support accumulate functions in this embodiment, and a cascade input port connected to the output port of an upstream slice to support cascading.
대표청구항
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What is claimed is: 1. An integrated circuit comprising: a plurality of digital signal processing (DSP) elements, including a first DSP element and a second DSP element, each of the first DSP element and the second DSP element having substantially identical structure and each of the first DSP eleme
What is claimed is: 1. An integrated circuit comprising: a plurality of digital signal processing (DSP) elements, including a first DSP element and a second DSP element, each of the first DSP element and the second DSP element having substantially identical structure and each of the first DSP element and the second DSP element comprising a respective switch connected to a respective hardwired adder; a first signal line and a second signal line connecting the first DSP element to the second DSP element; the first signal line connecting a first output cascade port of the first DSP element to a first input cascade port of the second DSP element; the second signal line connecting a second output cascade port of the first DSP element to a second input cascade port of the second DSP element; the first output cascade port being on an input side of a multiplier of the first DSP element; the first input cascade port being on an input side of a multiplier of the second DSP element; the second output cascade port being on an output side of both the hardwired adder of the first DSP element and the multiplier of the first DSP element; and the second input cascade port being on an input side of the hardwired adder of the second DSP element and on an output side of the multiplier of the second DSP element; wherein the first DSP element is connected to the second DSP element for cascading thereof on pre-and post-multiplier sides of the second DSP element. 2. The integrated circuit of claim 1 wherein the switch of the first DSP element comprises a multiplexer configured to select input for the hardwired adder of the first DSP element. 3. The integrated circuit of claim 2 wherein the multiplexer of the first DSP element has a select line connected to a register of the first DSP element. 4. The integrated circuit of claim 2 wherein the multiplier of the first DSP element is hardwired and is connected to the multiplexer of the first DSP element. 5. The integrated circuit of claim 1 further comprising a configurable logic block of a programmable logic device. 6. The integrated circuit of claim 5 further comprising a programmable interconnect of the programmable logic device connected to the first DSP element. 7. An integrated circuit comprising: a plurality of digital signal processing (DSP) elements, including a first DSP element and a second DSP element, each of the first DSP element and the second DSP element having substantially identical structure and each of the first DSP element and the second DSP element comprising a respective switch connected to a respective hardwired adder; a first signal line and a second signal line connecting the first DSP element to the second DSP element; the first signal line connecting a first output cascade port of the first DSP element to a first input cascade port of the second DSP element; the second signal line connecting a second output cascade port of the first DSP element to a second input cascade port of the second DSP element; the first output cascade port being on an input side of a multiplier of the first DSP element; the first input cascade port being on an input side of a multiplier of the second DSP element; the second output cascade port being on an output side of both the hardwired adder of the first DSP element and the multiplier of the first DSP element; and the second input cascade port being on an input side of the hardwired adder of the second DSP element and on an output side of the multiplier of the second DSP element; wherein the first DSP element is connected to the second DSP element for cascading thereof on pre-and post-multiplier sides of the second DSP element without having to pass through programmable interconnects of a programmable logic device. 8. The integrated circuit of claim 7 wherein the switch of the first DSP element comprises a multiplexer. 9. The integrated circuit of claim 8 wherein the multiplexer of the first DSP element has a select line connected to a register of the first DSP element. 10. The integrated circuit of claim 8 wherein the multiplexer of the first DSP element has a select line connected to a configuration memory cell. 11. The integrated circuit of claim 7 wherein the multiplier of the first DSP element is connected to the switch of the first DSP element. 12. The integrated circuit of claim 7 wherein the first DSP element further comprises a feedback port, wherein the feedback port is connected to the second output cascade port of the first DSP element. 13. The integrated circuit of claim 7 further comprising a common register connected to the first DSP element and the second DSP element. 14. The integrated circuit of claim 7, wherein the plurality of DSP elements have output ports connected to programmable interconnect circuitry having buses and settable switches coupled thereto. 15. The integrated circuit of claim 7, wherein the plurality of DSP elements each have at least one operand input port connected to the programmable interconnect circuitry. 16. The integrated circuit of claim 7, wherein the first DSP element further includes: a first operand input port; a second operand input port; and a third operand input port. 17. The integrated circuit of claim 16, further comprising an operand register connected for receiving data from the programmable interconnect circuitry and connected for transmitting the data on the third operand input port. 18. The integrated circuit of claim 16, further comprising a multiplexer connected to an operand register, the multiplexer configured for selecting either a first connection between interconnect circuitry and the third operand input port or a second connection between the operand register and the third operand input port. 19. The integrated circuit of claim 16, wherein the second DSP element further comprises a fourth operand input port connected to the third operand input port of the first DSP element. 20. The integrated circuit of claim 19, wherein the third operand input port of the first DSP element directly connects to the fourth input port of the second DSP element. 21. The integrated circuit of claim 7, wherein at least one of the plurality of DSP elements further has a control signal port connected for receiving at least one set of DSP control signals. 22. The integrated circuit of claim 21, wherein the at least one set of DSP control signals specifies a portion of a digital filter. 23. The integrated circuit of claim 21, wherein the control signal port receives a plurality of sequential sets of DSP control signals. 24. The integrated circuit of claim 23, wherein the plurality of sequential sets of DSP control signals includes a first set of DSP control signals specifying a first portion of a DSP operation and a second set of DSP control signals specifying a second portion of the DSP operation. 25. The integrated circuit of claim 24, wherein the first portion of the DSP operation includes a multiply step and the second portion of the DSP operation includes an accumulate step. 26. The integrated circuit of claim 21, wherein the at least one of the plurality of DSP elements further includes a mode register configured for storing the at least one set of DSP control signals. 27. The integrated circuit of claim 21, wherein the integrated circuit is a programmable logic device having a plurality of configurable logic blocks, the plurality of configurable logic blocks configured to provide a state machine, and wherein the state machine issues the DSP control signals. 28. The integrated circuit of claim 21, wherein the integrated circuit is a programmable logic device having an embedded processor, and wherein the embedded processor issues the DSP control signals. 29. An integrated circuit comprising: configurable logic blocks; programmable interconnect circuitry connecting to some of the configurable logic blocks; the configurable logic blocks configurable for issuing signals to a digital signal processing (DSP) slice and connectable to the DSP slice via the programmable interconnect circuitry; the DSP slice comprising: a feedback port; a DSP-slice output port; and a direct connection between the DSP-slice output port and the feedback port; a first signal line and a second signal line for connecting the DSP slice to an upstream DSP slice; the first signal line connecting the DSP-slice output port of the DSP slice to a DSP-slice input port of the upstream DSP slice; the second signal line connecting an output cascade port of the DSP slice to an input cascade port of the upstream DSP slice; the output cascade port being on an input side of a multiplier of the DSP slice; the input cascade port being on an input side of a multiplier of the upstream DSP slice; the DSP-slice output port being on an output side of both a hardwired adder of the DSP slice and the multiplier of the DSP slice; and the DSP-slice input port being on an input side of a hardwired adder of the upstream DSP slice and on an output side of the multiplier of the upstream DSP slice; wherein the DSP slice is connected to the upstream DSP slice for cascading thereof on pre-and post-multiplier sides of the upstream DSP slice without having to pass through programmable interconnects of the programmable interconnect circuitry. 30. The integrated circuit of claim 29, further comprising a plurality of DSP tiles, wherein each DSP tile includes at least two DSP slices. 31. A circuit comprising: a plurality of DSP slices, including an upstream DSP slice and a downstream DSP slice, each of the upstream and downstream DSP slices including: a cascade input port; a DSP-slice input port; a DSP-slice output port; a cascade output port; first and second operand input ports; a product generator having a multiplier port connected to the first operand input port, a multiplicand port connected to the second operand input port, and a product port; and an adder having a first addend port connected to the product port, a second addend port connected to the cascade input port, and a sum port; a first signal line and a second signal line for connecting the downstream DSP slice to the upstream DSP slice; the first signal line connecting the DSP-slice output port of the downstream DSP slice to the DSP-slice input port of the upstream DSP slice; the second signal line connecting the cascade output port of the downstream DSP slice to the cascade input port of the upstream DSP slice; the cascade output port of the downstream DSP slice being on an input side of the product generator of the downstream DSP slice; the cascade input port of the upstream DSP slice being on an input side of the product generator of the upstream DSP slice; the DSP-slice output port of the downstream DSP slice being on an output side of both the adder of the downstream DSP slice and the product generator of the downstream DSP slice; and the DSP-slice input port of the upstream DSP slice being on an input side of the adder of the upstream DSP slice and on an output side of the product generator of the upstream DSP slice; wherein the downstream DSP slice is connected to the upstream DSP slice for cascading thereof on pre-and post-product generator sides of the upstream DSP slice without having to pass through programmable interconnects of programmable interconnect circuitry. 32. The circuit of claim 31, wherein the sum port of the upstream DSP slice connects to the cascade input port of the downstream DSP slice. 33. The circuit of claim 31, wherein the first operand port of the upstream DSP slice connects to one of the multiplier port and the multiplicand port of the downstream DSP slice. 34. The circuit of claim 33, wherein the product generator generates partial products. 35. The circuit of claim 31, wherein control circuitry is coupled to the upstream DSP slice and the downstream DSP slice for: issuing a first set of mode-control signals to the downstream DSP slice, the downstream DSP slice, wherein the first set of mode-control signals connects the first addend port of the downstream DSP slice to a constant; and issuing a second set of mode-control signals to the upstream DSP slice, wherein the second set of mode-control signals connects the first addend port of the upstream DSP slice to the DSP-slice output port of the downstream DSP slice. 36. The circuit of claim 35, wherein the constant is zero. 37. The circuit of claim 35, wherein the first and second operand input ports of the downstream DSP slice are for receiving respective first and second operands, and wherein at least one of the first and second sets of mode-control signals conveys the first operand to the first operand input port of the downstream DSP slice. 38. The circuit of claim 37, wherein the upstream DSP slice and the downstream DSP slice in combination instantiate a finite-impulse-response filter in response to the first and second sets of mode-control signals. 39. A system comprising: configurable logic blocks; interconnect lines; a plurality of switch matrices programmably connected to the interconnect lines; a column of DSP slices, each DSP slice including first and second operand input ports programmably connected to the interconnect lines via at least one of the switch matrices; a configuration memory storing configuration data defining a configuration of the logic blocks, switch matrices, and DSP slices of the column of DSP slices; a first signal line and a second signal line for connecting a downstream DSP slice to an adjacent upstream DSP slice in the column of DSP slices; the first signal line connecting a DSP-slice output port of the downstream DSP slice to a DSP-slice input port of the upstream DSP slice; the second signal line connecting a cascade output port of the downstream DSP slice to a cascade input port of the upstream DSP slice; the cascade output port being on an input side of a product generator of the downstream DSP slice; the cascade input port being on an input side of a product generator of the upstream DSP slice; the DSP-slice output port being on an output side of both an adder of the downstream DSP slice and the product generator of the downstream DSP slice; and the DSP-slice input port being on an input side of an adder of the upstream DSP slice and on an output side of a product generator of the upstream DSP slice; wherein the downstream DSP slice is connected to the upstream DSP slice for cascading thereof on pre-and post-product generator sides of the upstream DSP slice without having to pass through the plurality of switch matrices programmably connected to the interconnect lines. 40. The system of claim 39, further comprising DSP tiles, each DSP tile includes a pair of DSP slices. 41. A DSP element in an integrated circuit comprising: a first switch; a multiplier circuit connected to the first switch; a second switch, the second switch connected to the multiplier circuit; an adder circuit connected to the second switch; wherein the integrated circuit comprises another DSP element having substantially identical structure to the DSP element and is coupled to the DSP element via dedicated signal lines including: a first signal line and a second signal line for connecting the DSP element to the other DSP element; the first signal line connecting a DSP-element output port of the DSP element to a DSP-element input port of the other DSP element; the second signal line connecting a cascade output port of the DSP element to a cascade input port of the other DSP element; the cascade output port being on an input side of the multiplier circuit of the DSP element; the cascade input port being on an input side of the multiplier circuit of the other DSP element; the DSP-element output port being on an output side of both the adder circuit of the DSP element and the multiplier circuit of the DSP element; and the DSP-element input port being on an input side of the adder circuit of the other DSP element and on an output side of the multiplier circuit of the other DSP element; wherein the DSP element is connected to the other DSP element for cascading thereof on pre-and post-multiplier circuit sides of the other DSP element without having to pass through programmable interconnects of programmable interconnect circuitry of the integrated circuit. 42. The DSP element of claim 41 wherein the first switch is connected either to a configuration memory cell or a register. 43. The DSP element of claim 42 wherein the second switch is connected either to a configuration memory cell or a register. 44. The DSP element of claim 43, wherein the second switch is connected to the register, and wherein a switching speed of the second switch is capable of being equal to an input data rate of the DSP element.
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