Data transfer control device including a switch circuit that switches write destination of received packets
원문보기
IPC분류정보
국가/구분
United States(US) Patent
등록
국제특허분류(IPC7판)
G06F-003/00
H04L-012/56
출원번호
US-0378466
(2006-03-20)
등록번호
US-7475171
(2009-01-06)
우선권정보
JP-2005-083540(2005-03-23)
발명자
/ 주소
Honda,Hiroyasu
출원인 / 주소
Seiko Epson Corporation
대리인 / 주소
Oliff & Berridge PLC
인용정보
피인용 횟수 :
3인용 특허 :
4
초록▼
A data transfer control device including: a link controller which analyzes a packet received through a serial bus; a packet detection circuit which detects completion or start of packet reception based on analysis result of the received packet; first and second packet buffers into which the packet r
A data transfer control device including: a link controller which analyzes a packet received through a serial bus; a packet detection circuit which detects completion or start of packet reception based on analysis result of the received packet; first and second packet buffers into which the packet received through the serial bus is written; and a switch circuit which switches a write destination of the received packet. When a Kth packet has been written into one of the first and second packet buffers and completion of reception of the Kth packet or start of reception of a (K+1)th packet subsequent to the Kth packet has been detected, the switch circuit switching the write destination of the (K+1)th packet to the other of the first and second packet buffers.
대표청구항▼
What is claimed is: 1. A data transfer control device that controls data transfer, the data transfer control device comprising: a link controller that analyzes a packet received through a serial bus; a packet detection circuit that detects completion or start of packet reception based on analysis r
What is claimed is: 1. A data transfer control device that controls data transfer, the data transfer control device comprising: a link controller that analyzes a packet received through a serial bus; a packet detection circuit that detects completion or start of packet reception based on analysis result of the received packet; first and second packet buffers into which the packet received through the serial bus is written; and a switch circuit that switches a write destination of the received packet, when a Kth packet has been written into one of the first and second packet buffers and completion of reception of the Kth packet or start of reception of a (K+1)th packet subsequent to the Kth packet has been detected, the switch circuit switching the write destination of the (K+1)th packet to the other of the first and second packet buffers. 2. The data transfer control device as defined in claim 1, when the packet received through the serial bus is a read request packet, the link controller sets the first packet buffer as a reception packet buffer and sets the second packet buffer as a transmission packet buffer, and when the packet received through the serial bus is a write request packet, the link controller sets the first and second packet buffers as reception packet buffers between which the write destination is switched by the switch circuit. 3. The data transfer control device as defined in claim 2, the write request packet including a response request field used for indicating whether or not to perform handshake transfer using an acknowledge packet, and when the packet received through the serial bus is the write request packet and a response request value "response not requested" is set in the response request field, the link controller sets the first and second packet buffers as the reception packet buffers between which the write destination is switched by the switch circuit. 4. The data transfer control device as defined in claim 1, comprising: an interface circuit that performs interface processing between the data transfer control device and a display driver connected to the data transfer control device through an interface bus; and a signal detection circuit that detects a vertical synchronization signal used for indicating a non-display period of a display panel and outputs a detection signal when the vertical synchronization signal has been input from the display driver, when the link controller has received a read request packet that requests reading of status of the vertical synchronization signal, the link controller sets the first packet buffer as a reception packet buffer and sets the second packet buffer as a transmission packet buffer, waits for the detection signal to be output from the signal detection circuit, and, on condition that the detection signal has been output from the signal detection circuit, reads a response packet or an acknowledge packet for the read request packet from the second packet buffer set as the transmission packet buffer and transmits the response packet or the acknowledge packet through the serial bus. 5. The data transfer control device as defined in claim 2, comprising: an interface circuit that performs interface processing between the data transfer control device and a display driver connected to the data transfer control device through an interface bus; and a signal detection circuit that detects a vertical synchronization signal used for indicating a non-display period of a display panel and outputs a detection signal when the vertical synchronization signal has been input from the display driver, when the link controller has received a read request packet that requests reading of status of the vertical synchronization signal, the link controller sets the first packet buffer as a reception packet buffer and sets the second packet buffer as a transmission packet buffer, waits for the detection signal to be output from the signal detection circuit, and, on condition that the detection signal has been output from the signal detection circuit, reads a response packet or an acknowledge packet for the read request packet from the second packet buffer set as the transmission packet buffer and transmits the response packet or the acknowledge packet through the serial bus. 6. The data transfer control device as defined in claim 4, when the link controller has received the read request packet, the link controller generates the response packet or the acknowledge packet for the read request packet, writes the generated response packet or acknowledge packet into the second packet buffer set as the transmission packet buffer, and, on condition that the detection signal has been output from the signal detection circuit, reads the response packet or the acknowledge packet written into the second packet buffer from the second packet buffer and transmits the response packet or the acknowledge packet through the serial bus. 7. The data transfer control device as defined in claim 4, when the link controller has received a write request packet that requests writing of a command or data after the response packet or the acknowledge packet has been transmitted through the serial bus, the link controller sets the first and second packet buffers as the reception packet buffers between which the write destination is switched by the switch circuit, and outputs the command or the data for which writing has been requested to the interface circuit through one of the first and second packet buffers, and the interface circuit outputting the command or the data from the link controller to the display driver through the interface bus. 8. The data transfer control device as defined in claim 7, the write request packet including a response request field used for indicating whether or not to perform handshake transfer using an acknowledge packet, a response request value "response not requested" being set in the response request field, and when the link controller has received the write request packet in which a response request value "response not requested" is set, the link controller outputs the command or the data for which writing has been requested to the interface circuit without directing transmission of the acknowledge packet for the write request packet. 9. The data transfer control device as defined in claim 4, comprising: an edge setting register that is used for setting whether to detect a rising edge or a falling edge of the vertical synchronization signal, the signal detection circuit outputs the detection signal on condition that the rising edge of the vertical synchronization signal has been detected when "rising edge detection" has been set in the edge setting register, and outputs the detection signal on condition that the falling edge of the vertical synchronization signal has been detected when "falling edge detection" has been set in the edge setting register. 10. The data transfer control device as defined in claim 4, comprising: a read register used for reading the status of the vertical synchronization signal, the read request packet that requests reading of the status of the vertical synchronization signal being a packet that requests reading from the read register. 11. The data transfer control device as defined in claim 4, the interface circuit being an MIPU interface circuit that generates an MPU interface signal. 12. The data transfer control device as defined in claim 1, the packet detection circuit detecting completion of reception of a packet based on a data length set in a header of the packet. 13. The data transfer control device as defined in claim 2, the packet detection circuit detecting completion of reception of a packet based on a data length set in a header of the packet. 14. The data transfer control device as defined in claim 4, the packet detection circuit detecting completion of reception of a packet based on a data length set in a header of the packet. 15. The data transfer control device as defined in claim 1, comprising: a transceiver that uses differential signal lines of the serial bus, and transmits and receives a packet to and from a host-side data transfer control device. 16. The data transfer control device as defined in claim 2, comprising: a transceiver that uses differential signal lines of the serial bus, and transmits and receives a packet to and from a host-side data transfer control device. 17. The data transfer control device as defined in claim 4, comprising: a transceiver that uses differential signal lines of the serial bus, and transmits and receives a packet to and from a host-side data transfer control device. 18. An electronic instrument comprising: the data transfer control device as defined in claim 1; and a display driver connected to the data transfer control device through an interface bus. 19. An electronic instrument comprising: the data transfer control device as defined in claim 2; and a display driver connected to the data transfer control device through an interface bus. 20. An electronic instrument comprising: the data transfer control device as defined in claim 4; and the display driver connected to the data transfer control device through the interface bus.
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이 특허에 인용된 특허 (4)
Kumar,Nishit; Vogt,Timothy, Flexible and scalable architecture for transport processing.
Foster Bradly J. (Ft. Collins CO) Hodge David J. (Loveland CO) Kommrusch Steven J. (Ft. Collins CO), Frame rate conversion with asynchronous pixel clocks.
Pfahler, Jürgen; Jentsch, Peter, Time-alignment apparatus and method for time-aligning data frames of a plurality of channels in a telecommunication system.
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