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Techniques are described for detecting error events in codewords detected from data signals transmitted via a communication system. The error events are detected with an error detection code that corresponds to one or more dominant error events for the communication system. The invention develops a

Techniques are described for detecting error events in codewords detected from data signals transmitted via a communication system. The error events are detected with an error detection code that corresponds to one or more dominant error events for the communication system. The invention develops a class of error detection codes to detect specific error events of known types. In some embodiments, the communication system comprises a recording system. The error detection coding method may be used in conjunction with error correction processing to provide substantial performance gain compared to conventional parity-based post processing methods. For example, the error correction processing may include one or more correlation filters that correspond to the one or more dominant error events for the communication system. A correction module may correct the codeword based on a type of the detected error event and a location of the detected error event in the codeword.

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The invention claimed is: 1. A method comprising detecting an occurrence of an error event in a codeword with an error detection code that corresponds to one or more dominant error events prescribed for a communication system, wherein the error detection code uses a parity check matrix that include

The invention claimed is: 1. A method comprising detecting an occurrence of an error event in a codeword with an error detection code that corresponds to one or more dominant error events prescribed for a communication system, wherein the error detection code uses a parity check matrix that includes a plurality of rows of periodic parity check sum patterns for detecting the error events, each of the periodic parity check sum patterns comprising a repetitive binary pattern with a length of n bits. 2. The method of claim 1, wherein detecting the occurrence of the error event comprises detecting the occurrence of the error event at least partially within the codeword. 3. The method of claim 1, wherein the error event is of the form ±{+-}, ±{+-0+-}, ±{+-0+-0+-}, or ±{+-0 0+-}, wherein ±{+-} indicates an erroneous change in two consecutive bit values, ±{+-0+-} indicates an erroneous change in two consecutive bit values, followed by a correct bit value, and then followed by an erroneous change in two consecutive bit values, ±{+-0+-0+-} indicates an erroneous change in two consecutive bit values, followed by a correct bit value, followed by an erroneous change in two consecutive bit values, followed by a correct bit value, followed by an erroneous change in two consecutive bit values, and ±{+-0 0+-} indicates an erroneous change in two consecutive bit values, followed by two consecutive correct bit values, and then followed by an erroneous change in two consecutive bit values. 4. The method of claim 1, wherein the error event is of the form ±{+-}, ±{+-+}, ±{+-+-}, ±{+-+-+}, ±{+-+-+-}, or ±{+-0+-}, wherein ±{+-} indicates an erroneous change in two consecutive bit values, ±{+-+} indicates an erroneous change in three consecutive bit values, ±{+-+-} indicates an erroneous change in four consecutive bit values, ±{+-+-+} indicates an erroneous change in five consecutive bit values, ±{+-+-+-} indicates an erroneous change in six consecutive bit values, and ±{+-0+-} indicates an erroneous change in two consecutive bit values, followed by one correct bit value, and then followed by an erroneous change in two consecutive bit values. 5. The method of claim 1, wherein the error event comprises an even number of erroneous bits. 6. The method of claim 1, wherein each of the parity check sum patterns corresponds to a single dominant error event. 7. The method of claim 6, wherein a period of each parity check sum pattern is equal to a length of the corresponding dominant error. 8. The method of claim 6, wherein at least two parity check sum patterns in the parity check matrix correspond to a same dominant error event, and wherein one of the at least two parity check sum patterns comprises a shifted version of the other parity check sum pattern. 9. The method of claim 1, wherein n is equal to a length of a data word, and wherein each of the rows of the parity check matrix further includes one or more parity bits appended to the corresponding periodic parity check sum pattern of the row. 10. The method of claim 9, wherein the echelon canonical form is imposed on the parity check matrix while ensuring error detection capability in a parity zone defined by the one or more parity bits. 11. The method of claim 9, wherein the one or more parity bits appended to the periodic parity check sum patterns of the rows form an identity matrix. 12. The method of claim 1, further comprising detecting the codeword from a data sequence transmitted via the communication system. 13. The method of claim 1, wherein the codeword comprises a data word encoded with one or more parity bits. 14. The method of claim 1, further comprising determining a type of the detected error event and a location of the detected error event in the codeword. 15. The method of claim 14, wherein determining the type and the location of the detected error event comprises: applying the codeword to one or more error correlation filters that correspond to the one or more dominant error events; selecting a maximum likelihood error event based on output of the one or more error correlation filters; and selecting a position that corresponds to the selected error event. 16. The method of claim 15, wherein applying the codewords to the error correlation filters comprise activating only the error correlation filters that correspond to the type of the detected error event indicated by the parity check equations. 17. The method of claim 14, further comprising correcting the detected error event based on the type of the detected error event and the location of the detected error event in the codeword. 18. The method of claim 1, wherein the communication system comprises a data recording system. 19. The method of claim 1, wherein the communication system comprises a perpendicular magnetic data recording system. 20. The method of claim 1, wherein the communication system comprises a magnetic recording system, and the error detection code corresponds to one or more dominant error events prescribed for the magnetic recording system. 21. The method of claim 1, further comprising reading data from a magnetic medium, encoding the data, and detecting the codeword from the encoded data, wherein the error detection code corresponds to one or more dominant error events prescribed for a magnetic recording system. 22. The method of claim 1, wherein n is equal to a length of the codeword. 23. A processor comprising an error event detector to detect an occurrence of an error event in a codeword with an error detection code that corresponds to one or more dominant error events prescribed for a communication system, wherein the error detection code uses a parity check matrix that includes a plurality of rows of periodic parity check sum patterns for detecting the error events, each of the periodic parity check sum patterns comprising a repetitive binary pattern with a length of n bits. 24. The processor of claim 23, wherein the error event detector detects the occurrence of the error event at least partially within the codeword. 25. The processor of claim 23, wherein the error event is of the form ±{+-}, ±{+-0+-}, ±{+-0+-0+-}, or ±{+-0 0+-}, wherein ±{+-} indicates an erroneous change in two consecutive bit values, ±{+-0+-} indicates an erroneous change in two consecutive bit values, followed by a correct bit value, and then followed by an erroneous change in two consecutive bit values, ±{+-0+-0+-} indicates an erroneous change in two consecutive bit values, followed by a correct bit value, followed by an erroneous change in two consecutive bit values, followed by a correct bit value, followed by an erroneous change in two consecutive bit values, and ±{+-0 0+-} indicates an erroneous change in two consecutive bit values, followed by two consecutive correct bit values, and then followed by an erroneous change in two consecutive bit values. 26. The processor of claim 23, wherein the error event is of the form ±{+-}, ±{+-+}, ±{+-+-}, ±{+-+-+}, ±{+-+-+-}, or ±{+-0+-}, wherein ±{+-} indicates an erroneous change in two consecutive bit values, ±{+-+} indicates an erroneous change in three consecutive bit values, ±{+-+-} indicates an erroneous change in four consecutive bit values, ±{+-+-+} indicates an erroneous change in five consecutive bit values, ±{+-+-+-} indicates an erroneous change in six consecutive bit values, and ±{+-0+-} indicates an erroneous change in two consecutive bit values, followed by one correct bit value, and then followed by an erroneous change in two consecutive bit values. 27. The processor of claim 23, wherein each of the parity check sum patterns corresponds to a single dominant error event. 28. The processor of claim 27, wherein a period of each parity check sum pattern is equal to a length of the corresponding dominant. 29. The processor of claim 23, wherein n is equal to a length of a data word, and wherein each row of the parity check further includes one or more parity bits appended to the corresponding parity check sum pattern of the row. 30. The processor of claim 29, wherein the one or more parity bits appended to the periodic parity check sum patterns of the rows form an identity matrix. 31. The processor of claim 29, wherein the echelon canonical form is imposed on the parity check matrix while ensuring error detection capability in a parity zone defined by the one or more parity bits. 32. The processor of claim 29, wherein at least two parity check sum patterns correspond to a same dominant error event, and wherein one of the at least two parity check sum patterns comprises a shifted version of the other parity check sum pattern. 33. The processor of claim 23, further comprising one or more error correlation filters to determine a type of the detected error event and a location of the detected error event in the codeword, wherein the one or more error correlation filters correspond to the one or more dominant error events. 34. The processor of claim 33, further comprising a maximum value selector to select a maximum likelihood error event and a corresponding position based on output of the one or more error correlation filters. 35. The processor of claim 33, further comprising a correction module to correct the detected error event based on the type of the detected error event and the location of the detected error event in the codeword. 36. The processor of claim 33, wherein applying the codewords to the error correlation filters comprise activating only the error correlation filters that correspond to the type of the detected error event indicated by the parity check equations. 37. The processor of claim 23, wherein the communication system comprises a recording system. 38. The processor of claim 37, wherein the recording system comprises a perpendicular recording system. 39. The processor of claim 23, wherein the communication system comprises a magnetic recording system, and the error detection code corresponds to one or more dominant error events prescribed for the magnetic recording system. 40. The processor of claim 23, wherein the communication system comprises a magnetic recording system, the processor is coupled to receive encoded data from an encoding module that encodes data read from a magnetic medium, and the processor is configured to detect the codeword from the encoded data. 41. The processor of claim 23, wherein n is equal to a length of the codeword. 42. A computer-readable medium comprising instructions that when executed in a processor detect an occurrence of an error event in a codeword with an error detection code that corresponds to one or more dominant error events prescribed for a communication system, wherein the error detection code uses a parity check matrix that includes a plurality of rows of periodic parity check sum patterns for detecting the error events, each of the periodic parity check sum patterns comprising a repetitive binary pattern with a length of n bits. 43. The computer-readable medium of claim 42, further comprising instructions that when executed in the processor: apply the codeword to one or more error correlation filters that correspond to the one or more dominant error events; select a maximum likelihood error event based on output of the one ore more error correlation filters to determine a type of the detected error event; and select a position that corresponds to the selected error event to determine a location of the detected error event in the codeword. 44. The computer-readable medium of claim 43, wherein applying the codewords to the error correlation filters comprise activating only the error correlation filters that correspond to the type of the detected error event indicated by the parity check equations. 45. The computer-readable medium of claim 42, further comprising instructions that when executed in the processor correct the detected error event based on the type of the detected error event and the location of the detected error event in the codeword. 46. The computer-readable medium of claim 42, wherein the communication system comprises a magnetic recording system, and the error detection code corresponds to one or more dominant error events prescribed for the magnetic recording system. 47. The computer-readable medium of claim 42, wherein the communication system comprises a magnetic recording system, and wherein the instructions cause the processor to receive encoded data from an encoding module that encodes data read from a magnetic medium, and detect the codeword from the encoded data.