초록 ▼

A memory subsystem includes a memory controller operable to generate first control signals according to a standard interface. A memory interface adapter is coupled to the memory controller and is operable responsive to the first control signals to develop second control signals adapted to be applied

A memory subsystem includes a memory controller operable to generate first control signals according to a standard interface. A memory interface adapter is coupled to the memory controller and is operable responsive to the first control signals to develop second control signals adapted to be applied to a memory subsystem to access desired storage locations within the memory subsystem.

대표청구항 ▼

What is claimed is: 1. A memory system, comprising: a memory controller operable to generate first control signals according to a standard interface, the memory controller further including an attachable behaviors circuit adapted to receive configuration data, the configuration data causing the att

What is claimed is: 1. A memory system, comprising: a memory controller operable to generate first control signals according to a standard interface, the memory controller further including an attachable behaviors circuit adapted to receive configuration data, the configuration data causing the attachable behaviors circuit to implement corresponding memory behaviors, and the attachable behaviors circuit operable in combination with the memory controller to generate memory addresses using the configuration data, the generated memory addresses defining the corresponding memory behaviors; a memory interface adapter coupled to the memory controller, the memory interface adapter operable responsive to the generated memory addresses to develop control signals adapted to access corresponding data storage locations; and the attachable behaviors circuitry is operable to execute corresponding memory behaviors without executing programming instructions. 2. The memory system of claim 1 further comprising a physical control layer and wherein the control signals from the memory interface adapter are applied through the physical control layer to access desired storage locations in the memory subsystem. 3. The memory system of claim 1 wherein the memory behaviors executed by the attachable behaviors circuitry includes generating memory addresses to stride through a portion of memory. 4. The memory system of claim 1 wherein the memory behaviors circuitry is formed in a field programmable gate array (FPGA). 5. A memory service layer component, comprising: a memory controller operable to generate first control signals; an attachable behaviors circuit coupled to the memory controller and adapted to receive configuration data to implement corresponding memory behaviors, the attachable behaviors circuit operable in combination with the memory controller to generate memory addresses using the configuration data, the generated memory addresses defining the corresponding memory behaviors and the memory addresses being part of the first control signals generated by the memory controller; a memory interface adapter coupled to the memory controller, the memory interface adapter operable responsive to the first control signals to develop second control signals adapted to access corresponding data storage locations; and the attachable behaviors circuitry is operable to execute corresponding memory behaviors without executing programming instructions. 6. The memory service layer component of claim 5 wherein the memory controller and attachable behaviors circuit include the same read and write state machine circuitry. 7. The memory service layer component of claim 5 wherein the memory controller includes a general read and general write state machine circuitry and wherein the attachable behaviors circuit includes separate attachable read and write state machines. 8. The memory service layer component of claim 5 further including a storage memory for storing configuration parameters and a plurality of registers for storing selected ones of the stored configuration parameters, wherein the parameters stored in the registers define a particular memory behavior implemented by the memory service layer. 9. A peer vector machine, comprising: a host processor; and a pipeline accelerator coupled to the host processor, the pipeline accelerator including at least one hardwired pipeline units operable to process data without executing programming instructions, and the accelerator further including a memory service layer component including a memory controller and an attachable behaviors circuit, the attachable behaviors circuit adapted to receive configuration data from the hardwired pipeline units, the configuration data causing the attachable behaviors circuit to implement corresponding memory behaviors, and the attachable behaviors circuit operable in combination with the memory controller to generate memory addresses using the configuration data, the generated memory addresses defining the corresponding memory behaviors. 10. The peer vector machine of claim 9 wherein the attachable behaviors circuit includes a stride value register for storing a stride value and circuitry for generating the memory addresses using the stored stride value. 11. The peer vector machine of claim 9 wherein the memory controller includes general read and general write state machine circuitry and wherein the attachable behaviors circuit includes separate attachable read and write state machine circuitry. 12. The peer vector machine of claim 9 wherein memory service layer further comprises a write index register, a write offset register, a read index register, and a read offset register, the first two of these registers storing data the attachable behaviors circuitry utilizes in generating memory addresses during write operations and the last two of these registers storing data the attachable behaviors circuitry utilizes in generating memory addresses during read operations. 13. The peer vector machine of claim 9 wherein the pipeline accelerator further comprises an input FIFO register coupled to the memory controller, the input FIFO register adapted to receive input data to be written into corresponding data storage locations in a memory subsystem. 14. The peer vector machine of claim 9 wherein the pipeline accelerator further comprises an output FIFO register coupled to the memory controller, the output FIFO register adapted to receive data read from corresponding memory locations in a memory subsystem. 15. A peer vector machine, comprising: a host processor; a pipeline accelerator coupled to the host processor, the pipeline accelerator including at least one hardwired pipeline units operable to process data without executing programming instructions, and the accelerator further including a memory service layer component including a memory controller and an attachable behaviors circuit, the attachable behaviors circuit adapted to receive configuration data from the hardwired pipeline units, the configuration data causing the attachable behaviors circuit to implement corresponding memory behaviors, and the attachable behaviors circuit operable in combination with the memory controller to generate memory addresses using the configuration data, the generated memory addresses defining the corresponding memory behaviors; a memory interface adapter coupled to the memory controller and operable to generate control signals responsive to the generated memory addresses; and a memory subsystem coupled to the memory interface adapter and operable to access data locations in the memory subsystem responsive to the control signals from the memory interface adapter. 16. The peer vector machine of claim 15 wherein the memory subsystem comprises SRAM. 17. The peer vector machine of claim 15 wherein the memory subsystem comprises DRAM. 18. The peer vector machine of claim 15 wherein the attachable behaviors circuit includes a stride value register for storing a stride value and circuitry for generating the memory addresses using the stored stride value. 19. The peer vector machine of claim 15 wherein the memory interface adapter is configurable to interface the memory controller to different memory subsystems.