Thread dispatch for multiprocessor computer systems
원문보기
IPC분류정보
국가/구분
United States(US) Patent
등록
국제특허분류(IPC7판)
G06F-009/46
G06F-015/173
G06F-015/16
출원번호
US-0068599
(2002-02-06)
등록번호
US-7487504
(2009-02-03)
발명자
/ 주소
Peterson,Ricky Merle
출원인 / 주소
International Business Machines Corporation
대리인 / 주소
Martin & Associates, LLC
인용정보
피인용 횟수 :
10인용 특허 :
14
초록▼
A thread dispatch mechanism dispatches threads in a multiprocessor computer system that has hardware multithreading enabled, thereby allowing each processor to execute multiple threads. The thread dispatch mechanism determines which processors are busy and cannot execute an additional thread, which
A thread dispatch mechanism dispatches threads in a multiprocessor computer system that has hardware multithreading enabled, thereby allowing each processor to execute multiple threads. The thread dispatch mechanism determines which processors are busy and cannot execute an additional thread, which processors are working on a thread but can still accept an additional thread, and which processors are idle. As threads are ready to be dispatched, each is dispatched to an idle processor instead of a processor that is already working on another thread. If there are no idle processors, the thread is dispatched to a processor working on one or more threads that can still process the new thread. In this manner the thread dispatch mechanism and method of the present invention provides greatly improved consistency in response times between threads and higher throughput compared to prior art methods of dispatching threads.
대표청구항▼
What is claimed is: 1. An apparatus for computer hardware multithreading comprising: a plurality of processors, each processor having hardware support for the capability of executing a plurality of threads; a memory coupled to the plurality of processors; a thread dispatch mechanism residing in the
What is claimed is: 1. An apparatus for computer hardware multithreading comprising: a plurality of processors, each processor having hardware support for the capability of executing a plurality of threads; a memory coupled to the plurality of processors; a thread dispatch mechanism residing in the memory and executed by at least one of the plurality of processors, the thread dispatch mechanism determining which of the plurality of processors are idle, which of the plurality of processors is busy processing a thread but can accept a new thread, and which of the plurality of processors cannot accept the new thread since it is working on a maximum number of threads the processor can execute and, the thread dispatch mechanism dispatching the new thread to an idle processor, if one exists; and wherein all processors are made busy with a first thread before dispatching a second thread to any processor. 2. The apparatus of claim 1 wherein, if none of the plurality of processors is idle and if at least one of the plurality of processors can accept the new thread, the thread dispatch mechanism dispatches the new thread to one of the plurality of processors that can accept the new thread. 3. The apparatus of claim 1 wherein, if all of the plurality of processors cannot accept the new thread, the thread dispatch mechanism waits for one of the plurality of processors to complete processing a thread, thereby becoming a processor that can accept the new thread, and then dispatches the thread to the processor that can accept the new thread. 4. A method for dispatching threads in a computer system that includes a plurality of processors that can each support hardware multithreading to execute a plurality of threads, the method comprising the steps of: (1) determining the status of each of the plurality of processors, wherein a processor is idle if not executing any threads, wherein the processor can accept a new thread if busy working on one or more threads but has the capacity to process the new thread, and wherein the processor cannot accept the new thread if busy working on a maximum number of threads the processor can execute; and (2) dispatching the new thread to an idle processor, if one exists, and wherein all processors are made busy with a first thread before dispatching a second thread to any processor. 5. The method of claim 4 further comprising the step of: if none of the plurality of processors is idle and if at least one of the plurality of processors can accept the new thread, the thread dispatch mechanism dispatches the new thread to one of the plurality of processors that can accept the new thread. 6. The method of claim 4 further comprising the steps of: if all of the plurality of processors cannot accept the new thread, the thread dispatch mechanism waits for one of the plurality of processors to complete processing a thread, thereby becoming a processor that can accept the new thread, and then dispatches the thread to the processor that can accept the new thread. 7. A computer-readable program product having storage media for storing a thread dispatch mechanism when executed by processor perform the step of: determining which of a plurality of processors in a hardware multithreading, multiprocessor computer system are idle, which of the plurality of processors is busy but can accept a new thread, and which of the plurality of processors cannot accept the new thread since it is working on a maximum number of threads the processor can execute, the thread dispatch mechanism dispatching the new thread to an idle processor, if one exists, wherein each processor can execute a plurality of threads; and wherein all processors are made busy with a first thread before dispatching a second thread to any processor. 8. The program product of claim 7 wherein, if none of the plurality of processors is idle and if at least one of the plurality of processors can accept the new thread, the thread dispatch mechanism dispatches the new thread to one of the plurality of processors that can accept the new thread. 9. The program product of claim 7 wherein, if all of the plurality of processors cannot accept the new thread, the thread dispatch mechanism waits for one of the plurality of processors to complete processing a thread, thereby becoming a processor that can accept the new thread, and then dispatches the new thread to the processor that can accept the new thread.
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이 특허에 인용된 특허 (14)
Brenner, Larry Bert; Browning, Luke Matthew, Apparatus and method for periodic load balancing in a multiple run queue system.
Dewey Pamela H. (Poughkeepsie NY) Glynn William J. (Poughkeepsie NY) Hough Roger E. (Highland NY) Rao Manohar R. (Poughkeepsie NY), Method and apparatus for dynamic work reassignment among asymmetric, coupled processors.
Barabash William (Acton MA) Yerazunis William S. (Hudson MA), Method apparatus for scheduling tasks in repeated iterations in a digital data processing system having multiple process.
Turner, Larry A.; Osberg, Edwin A.; McCoy, James Kevin, Method for allowing multiple processing threads and tasks to execute on one or more processor units for embedded real-time processor systems.
Chastain David M. (Plano TX) Mankovich James E. (Colorado Springs CO) Gostin Gary B. (Coppell TX), Multi-processor computer system having self-allocating processors.
Bono,Jean Pierre, Queues for soft affinity code threads and hard affinity code threads for allocation of processors to execute the threads in a multi-processor system.
Busaba, Fadi Y.; Carlough, Steven R.; Krygowski, Christopher A.; Prasky, Brian R.; Shum, Chung-Lung K., Management of resources within a computing environment.
Busaba, Fadi Y.; Carlough, Steven R.; Krygowski, Christopher A.; Prasky, Brian R.; Shum, Chung-Lung K., Management of resources within a computing environment.
Busaba, Fadi Y.; Carlough, Steven R.; Krygowski, Christopher A.; Prasky, Brian R.; Shum, Chung-Lung K., Management of resources within a computing environment.
Busaba, Fadi Y.; Carlough, Steven R.; Krygowski, Christopher A.; Prasky, Brian R.; Shum, Chung-Lung K., Management of resources within a computing environment.
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