초록 ▼

A high voltage generator includes a charge pump generating a high voltage in response to a pumping clock signal, a charge/discharge circuit responsive to the pumping clock signal and charging the high voltage to generate an output voltage, a comparator for comparing the output voltage with a referen

A high voltage generator includes a charge pump generating a high voltage in response to a pumping clock signal, a charge/discharge circuit responsive to the pumping clock signal and charging the high voltage to generate an output voltage, a comparator for comparing the output voltage with a reference voltage to generate a comparison result, and a clock modification circuit adjusting a pumping slope of the charge pump in relation to the comparison result, wherein the clock modification circuit reduces the pumping slope when the high voltage reaches a target voltage level.

대표청구항 ▼

What is claimed is: 1. A high voltage generator comprising: a charge pump generating a high voltage in response to a pumping clock signal; a charge/discharge circuit responsive to the pumping clock signal and charging the high voltage to generate an output voltage; a comparator for comparing the ou

What is claimed is: 1. A high voltage generator comprising: a charge pump generating a high voltage in response to a pumping clock signal; a charge/discharge circuit responsive to the pumping clock signal and charging the high voltage to generate an output voltage; a comparator for comparing the output voltage with a reference voltage to generate a comparison result; and a clock modification circuit adjusting a pumping slope of the charge pump in relation to the comparison result, wherein the clock modification circuit reduces the pumping slope when the high voltage reaches a target voltage level. 2. The high voltage generator circuit of claim 1, wherein the clock modification circuit reduces the pumping slope of the charge pump by at least one of changing a pulse width for the pumping clock signal, adjusting a frequency of the pumping clock signal, or adjusting an amplitude of the pumping clock signal. 3. The high voltage generator circuit of claim 2, wherein the clock modification circuit reduces the pumping slope of the charge pump in relation to a first and second phase of the pumping clock signal. 4. The high voltage generator circuit of claim 1, wherein the clock modification circuit comprises: a first inverter inverting a clock signal; a control circuit responsive to the comparison result and adjusting the speed with which the clock signal applied to the first inverter is inverted; and a second inverter inverting the output of the first inverter to generate the pumping clock signal. 5. The high voltage generator circuit of claim 1, wherein the clock modification circuit reduces the pumping slope by changing a driving capacitance value associated with the charge pump. 6. The high voltage generator circuit of claim 5, wherein the clock modification circuit comprises: a plurality of capacitors and a corresponding plurality of switches, wherein each one of the plurality of capacitors is selectively connected to a corresponding capacitor associated with the charge pump through a switching operation applied to the plurality of switches. 7. The high voltage generator circuit of claim 1, wherein the charge/discharge circuit comprises: a first charge/discharge circuit charging the high voltage received from the charge pump in response to a first phase of the pumping clock signal and generating the output voltage in response to a second phase of the pumping clock signal; and a second charge/discharge circuit supplying the output voltage from the first charge/discharge circuit to the comparator in response to the second phase of the pumping clock signal. 8. The high voltage generator circuit of claim 7, wherein the first charge/discharge circuit comprises: a first high voltage switch outputting the high voltage in response to the first phase of the pumping clock signal; a first capacitor charging the high voltage received from the first high voltage switch; and a second high voltage switch outputting a voltage charged in the first capacitor as the output voltage in response to the second phase of the pumping clock signal. 9. The high voltage generator circuit of claim 8, wherein the second charge/discharge circuit includes: a second capacitor outputting a voltage from the second high voltage switch to the comparator; and a discharge switch discharging a charged voltage in the second capacitor to ground in response to the first phase of the pumping clock signal, during a charging period of the first capacitor. 10. A flash memory device comprising: a memory cell array having a plurality of memory cells arranged in word lines and bit lines; and a high voltage generator circuit generating a high voltage supplied to a selected word line and comprising: a charge pump generating a high voltage in response to a pumping clock signal; a charge/discharge circuit responsive to the pumping clock signal and charging the high voltage to generate an output voltage; a comparator for comparing the output voltage with a reference voltage to generate a comparison result; and a clock modification circuit adjusting a pumping slope of the charge pump in relation to the comparison result, wherein the clock modification circuit reduces the pumping slope when the high voltage reaches a target voltage level. 11. The flash memory device of claim 10, wherein the clock modification circuit reduces the pumping slope of the charge pump by at least one of changing a pulse width for the pumping clock signal, adjusting a frequency of the pumping clock signal, or adjusting an amplitude of the pumping clock signal. 12. The flash memory device of claim 11, wherein the clock modification circuit reduces the pumping slope of the charge pump in relation to a first and second phase of the pumping clock signal. 13. The flash memory device of claim 10, wherein the clock modification circuit comprises: a first inverter inverting a clock signal; a control circuit responsive to the comparison result and adjusting the speed with which the clock signal applied to the first inverter is inverted; and a second inverter inverting the output of the first inverter to generate the pumping clock signal. 14. The flash memory device of claim 10, wherein the clock modification circuit reduces the pumping slope by changing a driving capacitance value associated with the charge pump. 15. The flash memory device of claim 14, wherein the clock modification circuit comprises: a plurality of capacitors and a corresponding plurality of switches, wherein each one of the plurality of capacitors is selectively connected to a corresponding capacitor associated with the charge pump through a switching operation applied to the plurality of switches. 16. The flash memory device of claim 10, wherein the charge/discharge circuit comprises: a first charge/discharge circuit charging the high voltage received from the charge pump in response to a first phase of the pumping clock signal and generating the output voltage in response to a second phase of the pumping clock signal; and a second charge/discharge circuit supplying the output voltage from the first charge/discharge circuit to the comparator in response to the second phase of the pumping clock signal. 17. The flash memory device of claim 16, wherein the first charge/discharge circuit comprises: a first high voltage switch outputting the high voltage in response to the first phase of the pumping clock signal; a first capacitor charging the high voltage received from the first high voltage switch; and a second high voltage switch outputting a voltage charged in the first capacitor as the output voltage in response to the second phase of the pumping clock signal. 18. The flash memory device of claim 17, wherein the second charge/discharge circuit includes: a second capacitor outputting a voltage from the second high voltage switch to the comparator; and a discharge switch discharging a charged voltage in the second capacitor to ground in response to the first phase of the pumping clock signal, during a charging period of the first capacitor.