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Pinning internal slack nodes to improve instruction scheduling 원문보기

IPC분류정보
국가/구분 United States(US) Patent 등록
국제특허분류(IPC7판)
  • G06F-009/45
출원번호 US-0929193 (2004-08-30)
등록번호 US-7493611 (2009-02-17)
발명자 / 주소
  • Martin,Allan Russell
출원인 / 주소
  • International Business Machines Corporation
대리인 / 주소
    Yee,Duke W.
인용정보 피인용 횟수 : 3  인용 특허 : 23

초록

A scheduling algorithm is provided for selecting the placement of instructions with internal slack into a schedule of instructions within a loop. The algorithm achieves this by pinning nodes with internal slack to corresponding nodes on the critical path of the code that have similar properties in

대표청구항

What is claimed is: 1. A method in a data processing system for scheduling a set of instructions, the method comprising: building a data dependency graph for the set of instructions, wherein a subset of the instructions form a critical path in the data dependency graph; identifying an internal slac

이 특허에 인용된 특허 (23)

  1. Michael S. Schlansker ; Vinod K. Kathail ; Greg Snider ; Shail Aditya Gupta ; Scott A. Mahlke ; Santosh Abraham, Automated design of processor systems using feedback from internal measurements of candidate systems.
  2. Odani Kensuke,JPX ; Tanaka Akira,JPX ; Tanaka Hirohisa,JPX, Compiler for optimizing memory instruction sequences by marking instructions not having multiple memory address paths.
  3. Ishizaki,Kauaki; Inagaki,Tatshushi; Komatsu,Hideaki, Compiling method, apparatus, and program.
  4. Christopher M. McKinsey ; Jayashankar Bharadwaj, Interactive instruction scheduling and block ordering.
  5. Danckaert, Koen; Catthoor, Francky, Loop optimization with mapping code on an architecture.
  6. Tirumalai Partha P. (Fremont CA), Method and apparatus for automatic selection of the load latency to be used in modulo scheduling in an optimizing compil.
  7. Tarsy Gregory (Scotts Valley CA) Woodard Michael J. (Fremont CA), Method and apparatus for cost-based heuristic instruction scheduling.
  8. Samra, Nicholas G.; Chinnakonda, Murali S., Method and apparatus for fast dependency coordinate matching.
  9. Tirumalai Partha P. ; Subramanian Krishna ; Baylin Boris, Method and apparatus for instruction scheduling in an optimizing compiler for minimizing overhead instructions.
  10. Kumar,Anoop; Nair,Sreekumar Ramakrishnan, Method and apparatus for integrated instruction scheduling and register allocation in a postoptimizer.
  11. Tarsy Gregory (Scotts Valley CA) Woodard Michael J. (Fremont CA), Method and apparatus for optimizing cost-based heuristic instruction scheduling.
  12. Subramanian Krishna, Method and apparatus for optimizing program loops containing omega-invariant statements.
  13. Subramanian Krishna ; Baylin Boris, Method and apparatus for time-reversed instruction scheduling with modulo constraints in an optimizing compiler.
  14. Nishiyama Hiroyasu,JPX ; Kikuchi Sumio,JPX, Method for compiling loops containing prefetch instructions that replaces one or more actual prefetches with one virtu.
  15. Powell Roger A. (1740 Hollins Rd. Bensalem PA 19020), Method for resource allocation and project control for the production of a product.
  16. Gupta Rajiv ; Worley ; Jr. William S., Out-of-order execution using encoded dependencies between instructions in queues to determine stall values that control.
  17. Heishi,Taketo; Takayama,Shuichi; Tanaka,Tetsuya; Ogawa,Hajime; Higaki,Nobuo, Processor, compiler and compilation method.
  18. Heishi, Taketo; Odani, Kensuke, Processor, compiling apparatus, and compile program recorded on a recording medium.
  19. Taketo Heishi JP; Kensuke Odani JP, Processor, compiling apparatus, and compile program recorded on a recording medium.
  20. Stark, IV,Jared W.; Brown,Mary D., Select-free dynamic instruction scheduling.
  21. Tzen,Ten H., Super-region instruction scheduling and code generation for merging identical instruction into the ready-to-schedule instruction.
  22. Damron, Peter C.; Kosche, Nicolai, System and method for scheduling instructions to maximize outstanding prefetches and loads.
  23. Chan Sun C. (Fremont CA) Dehnert James C. (Palo Alto CA) Lo Raymond W. (Sunnyvale CA) Towle Ross A. (San Francisco CA), System and method of generating object code using aggregate instruction movement.

이 특허를 인용한 특허 (3)

  1. Martin, Allan Russell, Extension of swing modulo scheduling to evenly distribute uniform strongly connected components.
  2. Bakowski, Ben, Method, apparatus and computer program for facilitating the improvement of a user interface.
  3. Martin, Allan Russell, Pinning internal slack nodes to improve instruction scheduling.
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