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Methods and apparatuses for allocating time slots to circuit switched channels 원문보기

IPC분류정보
국가/구분 United States(US) Patent 등록
국제특허분류(IPC7판)
  • H04J-003/16
출원번호 US-0673423 (1999-04-16)
등록번호 US-7496112 (2009-02-24)
우선권정보 SE-9801335(1998-04-17)
국제출원번호 PCT/SE99/000605 (1999-04-16)
§371/§102 date 20010201 (20010201)
국제공개번호 WO99/055036 (1991-10-28)
발명자 / 주소
  • Danielson,Magnus
  • Lindgren,Per
  • Wahlund,Thomas
출원인 / 주소
  • Net Insight AB
대리인 / 주소
    MacPherson Kwok Chen & Heid LLP
인용정보 피인용 횟수 : 21  인용 특허 : 15

초록

The present invention relates to methods and apparatuses for allocating time slots to circuit-switched channels established to comprise one or more respective time slots in a recurrent frame of a time division multiplexed network. According to the invention, a time slot allocated to said channel is

대표청구항

The invention claimed is: 1. In a time division multiplexed network in which a recurrent frame thereof is divided into time slots, and in which circuit-switched channels are allocated respective sets of time slots in said recurrent frame of said network, a method comprising: controlling the allocat

이 특허에 인용된 특허 (15)

  1. Beshai Maged E.,CAX ; Nichols Stacy W.,CAX ; Morris Todd D.,CAX, ATM service scheduler using reverse-binary scattering and time-space mapping.
  2. Schmidt Barnet M. ; Winkler Peter M., Automatic path selection for fiber-optic transmission networks.
  3. Kusano Toshihiko,JPX ; Suzuki Hiroshi,JPX, Communication network recoverable from link failure using prioritized recovery classes.
  4. Shtayer Ronen (Tel-Aviv ILX) Alon Naveh (Ranat Hashnron ILX) Alexander Joffe (Rehovot ILX), Method and apparatus for pacing asynchronous transfer mode (ATM) data cell transmission.
  5. Lindgren Per,SEX ; Bohm Christer,SEX ; Gauffin Lars,SEX ; Ramfelt Lars,SEX, Method and arrangement for dynamic signalling.
  6. Ramfelt Lars H.ang.kan ; Hidell Lars Markus,SEX, Method and device for dynamic synchronous transfer mode in a dual ring topology.
  7. Clanton Christopher Lamonte ; Smolinske Jeffrey Charles ; Tran Phieu Moc, Method, device, microprocessor and microprocessor memory for instantaneous preemption of packet data.
  8. Chan David Chi-Yin, Packet data transmission using dynamic channel assignment.
  9. Lindgren, Per; Bohm, Christer, Reallocation procedure.
  10. Bohm Christer,SEX ; Ramfelt Lars,SEX ; Lindgren Per,SEX ; Hidell Markus,SEX ; Sjodin Peter,SEX, Resource management scheme and arrangement.
  11. Nishimura Yasuyo (Tokyo JPX) Sakauchi Hideki (Tokyo JPX) Hasegawa Satoshi (Tokyo JPX), Self-healing network with distributed failure restoration capabilities.
  12. Driscoll Kevin R. (Maple Grove MN), Slotted arbitration without time jitter in a table driven protocol.
  13. Dambrackas William A. (Miami FL) Marshall Michael B. (Ft. Lauderdale FL) Greenstein Larry S. (Miami FL) Downie Alex (Cooper City FL), Statistical multiplexer with dynamic bandwidth allocation for asynchronous and synchronous channels.
  14. Graziano Michael J. (Warrenton VA) Hauris Jon F. (Manassas VA) Stanley Daniel L. (Manassas VA), Switching of multiple multimedia data streams.
  15. Beyda William J. ; Shaffer Shmuel, System and method for providing a droppable switched circuit.

이 특허를 인용한 특허 (21)

  1. Fourcand, Serge Francois, Aggregated link traffic protection.
  2. Fourcand, Serge Francois, Bandwidth reuse in multiplexed data stream.
  3. Fourcand, Serge Francois, Closed-loop clock synchronization.
  4. Fourcand, Serge Francois, Closed-loop clock synchronization.
  5. Rijpekema, Edwin, Data processing circuit wherein data processing units communicate via a network.
  6. Reddy, Nagareddy S., Delegation of mobile communication to external device.
  7. Fourcand, Serge Francois, Inter-packet gap network clock synchronization.
  8. Fourcand, Serge Francois, Inter-packet gap network clock synchronization.
  9. Livet, Catherine M.; Zuniga, Juan Carlos; Tomici, John L.; Rahman, Shamim Akbar, Method and apparatus for sharing slot allocation schedule information amongst nodes of a wireless mesh network.
  10. Fourcand, Serge Francois, Multi-component compatible data architecture.
  11. Fourcand, Serge Francois, Multi-component compatible data architecture.
  12. Fourcand, Serge Francois, Multi-frame network clock synchronization.
  13. Fourcand, Serge Francois, Multi-network compatible data architecture.
  14. Fourcand, Serge Francois, Multi-network compatible data architecture.
  15. Fourcand, Serge Francois, Multiplexed data stream circuit architecture.
  16. Fourcand, Serge Francois, Multiplexed data stream circuit architecture.
  17. Fourcand, Serge Francois, Multiplexed data stream payload format.
  18. Fourcand, Serge Francois, Network clock synchronization floating window and window delineation.
  19. Fourcand, Serge Francois, Network clock synchronization floating window and window delineation.
  20. Fourcand, Serge Francois, Network clock synchronization timestamp.
  21. Fourcand, Serge Francois, System for TDM data transport over Ethernet interfaces.
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