IPC분류정보
국가/구분 |
United States(US) Patent
등록
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국제특허분류(IPC7판) |
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출원번호 |
US-0549413
(2006-10-13)
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등록번호 |
US-7506106
(2009-03-17)
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발명자
/ 주소 |
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출원인 / 주소 |
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대리인 / 주소 |
Sterne, Kessler, Goldstein & Fox PLLC
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인용정보 |
피인용 횟수 :
5 인용 특허 :
20 |
초록
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A microprocessor has a data stream prefetch unit for processing a data stream prefetch instruction. The instruction specifies a data stream and a speculative stream hit policy indicator. If a load instruction hits in the data stream, then if the load is non-speculative the stream prefetch unit prefe
A microprocessor has a data stream prefetch unit for processing a data stream prefetch instruction. The instruction specifies a data stream and a speculative stream hit policy indicator. If a load instruction hits in the data stream, then if the load is non-speculative the stream prefetch unit prefetches a portion of the data stream from system memory into cache memory; however, if the load is speculative the stream prefetch unit selectively prefetches a portion of the data stream from the system memory into the cache memory based on the value of the policy indicator. The load instruction is speculative if it is not guaranteed to complete execution, such as if it follows a predicted branch instruction whose outcome has not yet been finally determined to be correct. In one embodiment, the stream prefetch unit performs a similar function for store instructions that hit in the data stream.
대표청구항
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I claim: 1. A method for prefetching a data stream into a microprocessor, comprising: decoding a prefetch instruction specifying a data stream, said prefetch instruction also specifying an indicator for specifying whether a speculative load instruction hitting in the data stream triggers prefetchin
I claim: 1. A method for prefetching a data stream into a microprocessor, comprising: decoding a prefetch instruction specifying a data stream, said prefetch instruction also specifying an indicator for specifying whether a speculative load instruction hitting in the data stream triggers prefetching of the data stream; decoding a load instruction that specifies an address within the data stream; determining whether the load instruction is speculative; prefetching, if the load instruction is not speculative, a portion of the data stream into the microprocessor; and selectively prefetching, if the load instruction is speculative, a portion of the data stream into the microprocessor based on whether said indicator specifies that a speculative load instruction hitting in the data stream triggers prefetching of the data stream, wherein the load instruction is speculative if it is not guaranteed to complete execution by the microprocessor, and wherein the load instruction is not guaranteed to complete because it follows a branch instruction whose outcome has been predicted and which has not yet been determined to be a correct predicted outcome. 2. The method as recited in claim 1, wherein said selectively prefetching a portion of the data stream into the microprocessor based on whether said indicator specifies that a speculative load instruction hitting in the data stream triggers prefetching of the data stream comprises prefetching the portion of the data stream into the microprocessor only if said indicator is a first predetermined value. 3. The method as recited in claim 1, wherein said selectively prefetching a portion of the data stream into the microprocessor based on whether said indicator specifies that a speculative load instruction hitting in the data stream triggers prefetching of the data stream comprises prefetching the portion of the data stream into the microprocessor unless said indicator is a first predetermined value. 4. The method as recited in claim 1, wherein said indicator further specifies whether a speculative store instruction hitting in the data stream triggers prefetching of the data stream, wherein the method further comprises: decoding a store instruction that specifies an address within the data stream; determining whether the store instruction is speculative; if the store instruction is not speculative, prefetching a portion of the data stream into the microprocessor; and if the store instruction is speculative, selectively prefetching a portion of the data stream into the microprocessor based on whether said indicator specifies that a speculative store instruction hitting in the data stream triggers prefetching of the data stream. 5. The method as recited in claim 1, wherein said prefetch instruction further specifies a fetch-ahead distance, wherein the method further comprises: suspending said prefetching and said selectively prefetching of said portion of the data stream into the microprocessor once a difference between a current prefetch address and said address specified by the load instruction is greater than said fetch-ahead distance. 6. The method as recited in claim 5, wherein said prefetch instruction further specifies a hysteresis amount, wherein the method further comprises: resuming said prefetching and said selectively prefetching of said portion of the data stream into the microprocessor once said difference is less than said fetch-ahead distance, wherein said resuming comprises prefetching at least said hysteresis amount of data before suspending prefetching again. 7. The method as recited in claim 1, wherein said prefetch instruction further specifies a locality characteristic, wherein said prefetching and said selectively prefetching comprise prefetching the data stream based on said locality characteristic. 8. The method as recited in claim 1, wherein said prefetch instruction further specifies a prefetch priority, wherein the method further comprises: generating a first one or more bus transaction requests on a bus coupling the microprocessor to a system memory to transfer data between the system memory and the microprocessor in response to said load instruction; generating a second one or more bus transaction requests on said bus to prefetch said portion of said data stream from the system memory to the microprocessor; and prioritizing said second one or more bus transaction requests relative to said first one or more bus transaction requests based on said prefetch priority. 9. The method as recited in claim 1, wherein said prefetch instruction further specifies an abnormal TLB access policy, wherein the method further comprises selectively aborting said prefetching said data stream based on said abnormal TLB access policy in response to an abnormal TLB access caused by said prefetching of said data stream. 10. The method as recited in claim 1, wherein said indicator is specified as immediate data within an operand field of said prefetch instruction. 11. The method as recited in claim 1, wherein said indicator is specified within a register of a register set of the microprocessor, wherein said register of said register set is specified within an operand field of said prefetch instruction. 12. The method as recited in claim 1, wherein said indicator is specified within a register of the microprocessor for controlling the state of the microprocessor. 13. The method as recited in claim 1, wherein said indicator is stored in a location in system memory, wherein an address of said location of said indicator in said system memory is specified within an operand field of said prefetch instruction. 14. The method as recited in claim 1, wherein said indicator is stored in a location in system memory, wherein an address of said location of said indicator in said system memory is specified within a register of a register set of the microprocessor. 15. A method for prefetching a data stream into a microprocessor, comprising: decoding a prefetch instruction specifying a data stream, a fetch-ahead distance, and a hysteresis amount, said prefetch instruction also specifying an indicator for specifying whether a speculative load instruction hitting in the data stream triggers prefetching of the data stream; decoding a load instruction that specifies an address within the data stream; determining whether the load instruction is speculative; prefetching, if the load instruction is not speculative, a portion of the data stream into the microprocessor; selectively prefetching, if the load instruction is speculative, a portion of the data stream into the microprocessor based on whether said indicator specifies that a speculative load instruction hitting in the data stream triggers prefetching of the data stream; suspending one of said prefetching and said selectively prefetching of said portion of said data stream once a difference between a current prefetch address and said address specified by the load instruction is greater than said fetch-ahead distance; and resuming one of said prefetching and said selectively prefetching of said portion of said data stream once said difference is less than said fetch-ahead distance, wherein said resuming comprises prefetching at least said hysteresis amount of data before suspending prefetching again. 16. A microprocessor coupled to a system memory, comprising: an instruction decoder, configured to decode a data stream prefetch instruction specifying a data stream in the system memory, said data stream prefetch instruction also specifying an indicator for specifying whether speculative load instructions hitting in said data stream trigger prefetching of said data stream; a load/store unit, coupled to said instruction decoder, configured to execute load instructions each specifying an address in the system memory; and a stream prefetch unit, coupled to said instruction decoder and to said load/store unit, configured to prefetch a portion of said data stream into a cache memory of the microprocessor, if said address of one of said load instructions hits in said data stream and if said load instruction is not speculative, wherein said stream prefetch unit is further configured to selectively prefetch a portion of said data stream into the cache memory based on said indicator, if said address hits in said data stream and if said load instruction is speculative, wherein said load instruction is speculative if it is not guaranteed to complete execution by the microprocessor, and wherein said load instruction is not guaranteed to complete because it follows a branch instruction whose outcome has been predicted and which has not yet been determined to be a correct predicted outcome. 17. The microprocessor as recited in claim 16, wherein said stream prefetch unit selectively prefetches said portion of the data stream into the cache memory only if said indicator is a first predetermined value. 18. The microprocessor as recited in claim 16, wherein said stream prefetch unit selectively prefetches said portion of the data stream into the cache memory unless said indicator is a first predetermined value. 19. The microprocessor as recited in claim 16, wherein said indicator further specifies whether speculative store instructions hitting in said data stream trigger prefetching of said data stream, wherein said stream prefetch unit is further configured to prefetch a portion of said data stream into the cache memory of the microprocessor if an address of one of said store instructions hits in said data stream and if said store instruction is not speculative, and wherein said stream prefetch unit is further configured to selectively prefetch a portion of said data stream into the cache memory based on said indicator if said address of said store instruction hits in said data stream and if said store instruction is speculative. 20. The microprocessor as recited in claim 16, wherein said data stream prefetch instruction further specifies a fetch-ahead distance, wherein said stream prefetch unit is further configured to suspend prefetching and selectively prefetching of said data stream into the cache memory once a difference between a current prefetch address and said address specified by the load instruction is greater than said fetch-ahead distance. 21. The microprocessor as recited in claim 20, wherein said data stream prefetch instruction further specifies a hysteresis amount, wherein said stream prefetch unit is further configured to resume prefetching and selectively prefetching of said data stream into the cache memory once said difference is less than said fetch-ahead distance, wherein when said stream prefetch unit resumes prefetching and selectively prefetching said data stream, said stream prefetch unit prefetches at least said hysteresis amount of data before suspending prefetching again. 22. The microprocessor as recited in claim 16, wherein said data stream prefetch instruction further specifies a locality characteristic, wherein said stream prefetch unit prefetches and selectively prefetches the data stream based on said locality characteristic. 23. The microprocessor as recited in claim 16, further comprising: a first translation look-aside buffer (TLB), coupled to said load/store unit, configured to cache virtual to physical page address translations of load/store requests generated by said load/store unit; and a second TLB, coupled to said stream prefetch unit, configured to cache virtual to physical page address translations of prefetch requests generated by said stream prefetch unit. 24. The microprocessor as recited in claim 16, wherein said stream prefetch unit comprises a plurality of stream prefetch engines, configured to prefetch a corresponding plurality of said data streams in response to a corresponding plurality of said data stream prefetch instructions. 25. The microprocessor as recited in claim 16, wherein said data stream prefetch instruction further specifies a prefetch priority, wherein the microprocessor further comprises a bus interface unit (BIU), coupled to said stream prefetch unit, configured to generate transaction requests on a bus coupling the microprocessor to the system memory to transfer data between the system memory and the microprocessor in response to requests generated by said load/store unit and said stream prefetch unit, wherein said BIU prioritizes said bus transaction requests for prefetching relative to said bus transaction requests for load instructions based on said prefetch priority. 26. The microprocessor as recited in claim 16, wherein said data stream prefetch instruction further specifies an abnormal TLB access policy, wherein the microprocessor further comprises a memory subsystem, comprising the cache memory and having a translation look-aside buffer (TLB), coupled to said stream prefetch unit, configured to selectively abort prefetching said data stream based on said abnormal TLB access policy in response to an abnormal TLB access caused by said prefetching of said data stream. 27. The microprocessor as recited in claim 16, wherein said indicator is specified as immediate data within an operand field of said data stream prefetch instruction. 28. The microprocessor as recited in claim 16, further comprising a register set, wherein said indicator is specified within a register of said register set, wherein said register of said register set is specified within an operand field of said data stream prefetch instruction. 29. The microprocessor as recited in claim 16, further comprising a register of the microprocessor for controlling the state of the microprocessor, wherein said indicator is specified within said register. 30. The microprocessor as recited in claim 16, wherein said indicator is stored in a location in system memory, wherein an address of said location of said indicator in said system memory is specified within an operand field of said data stream prefetch instruction. 31. The microprocessor as recited in claim 16, further comprising a register set, wherein said indicator is stored in a location in system memory, wherein an address of said location of said indicator in said system memory is specified within a register of said register set. 32. A microprocessor coupled to a system memory, comprising: an instruction decoder, configured to decode a data stream prefetch instruction specifying a data stream in the system memory, a fetch-ahead distance, and a hysteresis amount, said data stream prefetch instruction also specifying an indicator for specifying whether speculative load instructions hitting in said data stream trigger prefetching of said data stream; a load/store unit, coupled to said instruction decoder, configured to execute load instructions each specifying an address in the system memory; and a stream prefetch unit, coupled to said instruction decoder and to said load/store unit, configured to prefetch a portion of said data stream into a cache memory of the microprocessor, if said address of one of said load instructions hits in said data stream and if said load instruction is not speculative, wherein said stream prefetch unit is further configured to selectively prefetch a portion of said data stream into the cache memory based on said indicator, if said address hits in said data stream and if said load instruction is speculative, and wherein said stream prefetch unit is further configured to suspend one of said prefetching and said selectively prefetching of said portion of said data stream once a difference between a current prefetch address associated with said stream prefetch unit and said address specified by the load instruction is greater than said fetch-ahead distance, and is further configured to resume one of said prefetching and said selectively prefetching of said portion of said data stream once said difference is less than said fetch-ahead distance, wherein when said stream prefetch unit resumes one of said prefetching and said selectively prefetching said portion of said data stream, said stream prefetch unit prefetches at least said hysteresis amount of data before suspending one of said prefetching and said selectively prefetching again. 33. A computer program product for use with a computing device, the computer program product comprising: a tangible computer usable storage medium, having computer readable program code embodied thereon, for providing a microprocessor coupled to a system memory, said computer readable program code comprising: first computer readable program code for providing an instruction decoder, configured to decode a data stream prefetch instruction specifying a data stream in the system memory, a fetch-ahead distance, and a hysteresis amount, said data stream prefetch instruction also specifying an indicator for specifying whether speculative load instructions hitting in said data stream trigger prefetching of said data stream; second computer readable program code for providing a load/store unit, coupled to said instruction decoder, configured to execute load instructions each specifying an address in the system memory; and third computer readable program code for providing a stream prefetch unit, coupled to said instruction decoder and to said load/store unit, configured to prefetch a portion of said data stream into a cache memory of the microprocessor, if said address of one of said load instructions hits in said data stream and if said load instruction is not speculative, wherein said stream prefetch unit is further configured to selectively prefetch a portion of said data stream into the cache memory based on said indicator, if said address hits in said data stream and if said load instruction is speculative, and wherein said stream prefetch unit is further configured to suspend one of said prefetching and said selectively prefetching of said portion of said data stream once a difference between a current prefetch address associated with said stream prefetch unit and said address specified by the load instruction is greater than said fetch-ahead distance, and is further configured to resume one of said prefetching and said selectively prefetching of said portion of said data stream once said difference is less than said fetch-ahead distance, wherein when said stream prefetch unit resumes one of said prefetching and said selectively prefetching said portion of said data stream, said stream prefetch unit prefetches at least said hysteresis amount of data before suspending one of said prefetching and said selectively prefetching again. 34. The computer program product as recited in claim 33, wherein said indicator further specifies whether speculative store instructions hitting in said data stream trigger prefetching of said data stream, wherein said stream prefetch unit is further configured to prefetch a portion of said data stream into the cache memory of the microprocessor, if an said address of one of said store instructions hits in said data stream and if an store instruction is not speculative, wherein said stream prefetch unit is further configured to selectively prefetch a portion of said data stream into the cache memory based on said indicator, if said address of said store instruction hits in said data stream and if said store instruction is speculative. 35. The computer program product as recited in claim 33, wherein said data stream prefetch instruction further specifies a locality characteristic, wherein said stream prefetch unit prefetches and selectively prefetches the data stream based on said locality characteristic. 36. The computer program product as recited in claim 33, said computer readable program code further comprising: fourth computer readable program code for providing a first translation look-aside buffer (TLB), coupled to said load/store unit, configured to cache virtual to physical page address translations of load/store requests generated by said load/store unit; and fifth computer readable program code for providing a second TLB, coupled to said stream prefetch unit, configured to cache virtual to physical page address translations of prefetch requests generated by said stream prefetch unit. 37. The computer program product as recited in claim 33, wherein said stream prefetch unit comprises a plurality of stream prefetch engines, configured to prefetch a corresponding plurality of said data streams in response to a corresponding plurality of said data stream prefetch instructions. 38. The computer program product as recited in claim 33, wherein said data stream prefetch instruction further specifies a prefetch priority, said computer readable program code further comprising fourth computer readable program code for providing a bus interface unit (BIU), coupled to said stream prefetch unit, configured to generate transaction requests on a bus coupling the microprocessor to the system memory to transfer data between the system memory and the microprocessor in response to requests generated by said load/store unit and said stream prefetch unit, wherein said BIU prioritizes said bus transaction requests for prefetching relative to said bus transaction requests for load instructions based on said prefetch priority. 39. The computer program product as recited in claim 33, wherein said data stream prefetch instruction further specifies an abnormal TLB access policy, said computer readable program code further comprising fourth computer readable program code for providing a memory subsystem, comprising the cache memory and having a translation look-aside buffer (TLB), coupled to said stream prefetch unit, configured to selectively abort prefetching said data stream based on said abnormal TLB access policy in response to an abnormal TLB access caused by said prefetching of said data stream. 40. The computer program product as recited in claim 33, wherein said indicator is specified as immediate data within an operand field of said data stream prefetch instruction. 41. The computer program product as recited in claim 33, further comprising fourth computer readable program code for providing a register set, wherein said indicator is specified within a register of said register set, wherein said register of said register set is specified within an operand field of said data stream prefetch instruction. 42. The computer program product as recited in claim 33, further comprising fourth computer readable program code for providing a register of the microprocessor for controlling the state of the microprocessor, wherein said indicator is specified within said register. 43. The computer program product as recited in claim 33, wherein said indicator is stored in a location in system memory, and wherein an address of said location of said indicator in said system memory is specified within an operand field of said data stream prefetch instruction. 44. The computer program product as recited in claim 33, further comprising fourth computer readable program code for providing a register set, wherein said indicator is stored in a location in system memory, wherein an address of said location of said indicator in said system memory is specified within a register of said register set.
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